Embedded component device and manufacturing methods thereof

• US 9,406,658 B2
• Filed: 12/17/2010
• Issued: 08/02/2016
• Est. Priority Date: 12/17/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Chun-Che, Su, Yuan-Chang, Lee, Ming Chiang, Huang, Shih-Fu
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): Chang, Jay C
• Application Number:
  US12/972,046
• Publication Number:
  US 20120153493A1
• Time in Patent Office: 2,055 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

Claims

1. An embedded component device, comprising:

an electronic component including an electrical contact;

an upper patterned conductive layer;

a single dielectric layer between the upper patterned conductive layer and the electronic component, the dielectric layer having a first opening exposing the electrical contact;

a first electrical interconnect extending from the electrical contact to the upper patterned conductive layer, wherein the first electrical interconnect fills the first opening;

a lower patterned conductive layer embedded in the dielectric layer, the dielectric layer having a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer, the second opening having an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer;

a conductive via located at the lower portion of the second opening; and

a second electrical interconnect filling the upper portion of the second opening;

wherein the second electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and

wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

2. The embedded component device of claim 1, wherein the upper patterned conductive layer is electrically connected to the lower patterned conductive layer on a conductive path including the conductive via and the second electrical interconnect.

3. The embedded component device of claim 1, wherein the conductive via is a plated conductive post.

4. The embedded component device of claim 1, wherein a first distance from the upper surface of the conductive via to the upper patterned conductive layer is less than a second distance from an upper surface of the electronic component to the upper patterned conductive layer.

5. The embedded component device of claim 1, wherein the electronic component is at least one of an active component and a passive component.

6. The embedded component device of claim 1, wherein the dielectric layer includes at least one of a prepreg layer, a resin layer, and an epoxy layer.

7. The embedded component device of claim 6, wherein the dielectric layer includes fiber, and portions of the fiber are oriented away from the lower patterned conductive layer.

8. The embedded component device of claim 1, wherein the electronic component has a back surface, the back surface being disposed adjacent to the lower patterned conductive layer.

9. The embedded component device of claim 1, wherein the upper surface of the conductive via is substantially coplanar with an active surface of the electronic component.

10. An embedded component device, comprising:

an upper patterned conductive layer;

a lower patterned conductive layer;

an electronic component electrically connected to at least one of the upper patterned conductive layer and the lower patterned conductive layer;

a single dielectric layer between the upper patterned conductive layer and the lower patterned conductive layer and encapsulating the electronic component, the dielectric layer defining an opening extending from the lower patterned conductive layer to the upper patterned conductive layer, the lower patterned conductive layer embedded in the single dielectric layer;

a conductive via located at a lower portion of the opening and electrically connected to the lower patterned conductive layer; and

an electrical interconnect located at an upper portion of the opening and electrically connected to the upper patterned conductive layer;

wherein the electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and

wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

11. The embedded component device of claim 10, wherein the upper patterned conductive layer is electrically connected to the lower patterned conductive layer on a conductive path including the conductive via and the electrical interconnect.

12. The embedded component device of claim 10, wherein the conductive via is a conductive post.

13. The embedded component device of claim 10, wherein the first area is larger than the second area.

14. An embedded component device, comprising:

a first dielectric layer defining a cavity;

a lower patterned conductive layer disposed over the first dielectric layer;

an electronic component disposed in the cavity defined by the first dielectric layer;

a second dielectric layer encapsulating the electronic component, the second dielectric layer defining an opening extending through the second dielectric layer, the lower patterned conductive layer embedded in the second dielectric layer;

an upper patterned conductive layer disposed over the second dielectric layer;

a conductive via located at a lower portion of the opening and electrically connected to the lower patterned conductive layer; and

an electrical interconnect located at an upper portion of the opening and electrically connected to the upper patterned conductive layer;

wherein the electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and

wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

15. The embedded component device of claim 14, wherein an upper surface of the electronic component is recessed below an upper surface of the second dielectric layer.

16. The embedded component device of claim 14, wherein an active surface of the electronic component faces the upper patterned conductive layer.