System comprising a semiconductor device and structure

• US 9,406,670 B1
• Filed: 10/15/2014
• Issued: 08/02/2016
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk, Sekar, Deepak C., Wurman, Zeev
• Primary Examiner(s): Pert, Evan
• Application Number:
  US14/514,386
• Time in Patent Office: 657 Days
• US Class Current: 1/1
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/458 : for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 : using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66848 : with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/78639 : with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/812 : with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.

Claims

1. A semiconductor device, comprising:

a first layer comprising first transistors, said first transistors are interconnected by at least one metal layer comprising copper or aluminum;

a second layer comprising second transistors, said first layer is overlaid by said second layer,

wherein said second layer comprises a plurality of through layer vias having a diameter of less than 200 nm,

wherein said second transistors comprise a source contact, said source contact comprising a silicide, and

wherein said silicide has a sheet resistance of less than 15 ohm/sq.

2. A semiconductor device according to claim 1,

wherein at least two of said second transistors comprise connected gates.

3. A semiconductor device according to claim 1,

wherein at least two of said second transistors comprise a common source or a common drain.

4. A semiconductor device according to claim 1,

wherein said second transistors are lithographically aligned to said first transistors.

5. A semiconductor device according to claim 1,

wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.

6. A semiconductor device according to claim 1,

wherein said second transistors comprise a high k metal gate.

7. A semiconductor device according to claim 1, further comprising:

a re-useable donor wafer as a source of said second layer.

8. A semiconductor device according to claim 1, further comprising:

an isolation layer disposed between said first layer and said second layer.

9. A semiconductor device, comprising:

a first layer comprising first transistors, said first transistors are interconnected by at least one metal layer comprising copper or aluminum;

a second layer comprising second transistors, said first layer is overlaid by said second layer,

wherein said second layer comprises a plurality of through layer vias having a diameter of less than 200 nm, and

wherein at least two of said second transistors comprise connected gates.

10. A semiconductor device according to claim 9,

wherein said second transistors comprise a source contact, said source contact comprises a silicide.

11. A semiconductor device according to claim 9,

wherein at least two of said second transistors comprise a common source or a common drain.

12. A semiconductor device according to claim 9,

wherein said second transistors are lithographically aligned to said first transistors.

13. A semiconductor device according to claim 9,

wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.

14. A semiconductor device according to claim 9,

wherein said second transistors comprise a high k metal gate.

15. A semiconductor device according to claim 9, further comprising:

a re-useable donor wafer as a source of said second layer.

16. A semiconductor device according to claim 9, further comprising:

an isolation layer disposed between said first layer and said second layer.

17. A semiconductor device, comprising:

a first layer comprising first transistors, said first transistors are interconnected by at least one metal layer comprising copper or aluminum;

a second layer comprising second transistors, said first layer is overlaid by said second layer,

wherein said second layer comprises a plurality of through layer vias having a diameter of less than 200 nm, and

wherein at least two of said second transistors comprise a common source or a common drain.

18. A semiconductor device according to claim 17,

wherein said second transistors comprise a source contact, said source contact comprises a silicide.

19. A semiconductor device according to claim 17,

wherein at least two of said second transistors comprise connected gates.

20. A semiconductor device according to claim 17,

wherein said second transistors are lithographically aligned to said first transistors.

21. A semiconductor device according to claim 17,

wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors.

22. A semiconductor device according to claim 17, further comprising:

a re-useable donor wafer as a source of said second layer.

23. A semiconductor device according to claim 17, further comprising:

an isolation layer disposed between said first layer and said second layer.