Inductive structure formed using through silicon vias

• US 9,406,738 B2
• Filed: 07/20/2011
• Issued: 08/02/2016
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kireev, Vassili, Karp, James
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US13/187,234
• Publication Number:
  US 20130020675A1
• Time in Patent Office: 1,840 Days
• Field of Search: 257/499, 257/528, 257/531, 257/532, 257/520, 257/336, 257/724, 257/904, 257/924, 257/E21.022, 257/E29.166
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Claims

1. An inductor for an integrated circuit, the inductor comprising:

a first turn comprising a first through silicon via (TSV) coupled to a second TSV; and

a third TSV coupled to the second TSV, wherein;

the first TSV comprises a first end and a second end;

the second TSV comprises a first end and a second end;

the second end of the first TSV is coupled to the second end of the second TSV using a first conductive material;

the third TSV comprises a first end and a second end;

the first end of the third TSV is coupled to the first end of the second TSV using a second conductive material;

the first, second, and third TSVs are located within a first die; and

at least one of the first conductive material or the second conductive material is formed within a different die of the integrated circuit coupled to the first die;

wherein the inductor is solenoidal.

2. The inductor of claim 1, wherein:

the first end of the first TSV comprises an input node of the inductor; and

the second end of the third TSV comprises an output node of the inductor.

3. The inductor of claim 2, wherein the input node and the output node are located on opposing sides of the first die comprising the first, second, and third TSVs.

4. The inductor of claim 1, further comprising:

a fourth TSV comprising a first end and a second end,

wherein the second end of the third TSV is coupled to second end of the fourth TSV using a third conductive material.

5. The inductor of claim 4, wherein:

the first end of the first TSV comprises an input node of the inductor; and

the first end of the fourth TSV comprises an output node of the inductor.

6. The inductor of claim 5, wherein the input node of the inductor and the output node of the inductor are located on a same side of a die comprising the first, second, third, and fourth TSVs.

7. The inductor of claim 1, wherein:

the second conductive material comprises a metallization layer of the first die within which the first, second, and third TSVs are implemented; and

the first conductive material comprises a metallization layer of a second die, wherein the second die is the different die.

8. The inductor of claim 1, wherein:

the first conductive material comprises a metallization layer of the first die within which the first, second, and third TSVs are implemented; and

the second conductive material comprises a metallization layer of a second die, wherein the second die is the different die.

9. The inductor of claim 1, wherein:

the first, second, and third TSVs are implemented within the first die;

the first conductive material comprises a metallization layer of a second die coupled to the first die, wherein the second die is the different die; and

the second conductive material comprises a metallization layer of a third die coupled to the first die.

17. The inductor of claim 8, wherein

the first conductive material is a metallization layer within the second die;

and

the second conductive material is a metallization layer within a third die.

19. The inductor of claim 1, further comprising a solder ball coupling at least one of the TSVs to the at least one of the first conductive material or the second conductive material formed within the different die of the integrated circuit.

10. An integrated circuit structure, comprising:

an inductor, wherein the inductor is solenoidal and comprises;

a first through silicon via (TSV) comprising a first end and a second end located within a first die of the integrated circuit structure;

a second TSV comprising a first end and a second end located within the first die;

a first bottom formed of a first conductive material configured to couple the second end of the first TSV with the second end of the second TSV;

a third TSV comprising a first end and a second end located within the first die; and

a top formed of a second conductive material and configured to couple the first end of the second TSV with the first end of the third TSV;

wherein at least one of the first bottom or the top is formed within a different die of the integrated circuit structure coupled to the first die.

11. The integrated circuit structure of claim 10, wherein an input node of the inductor and an output node of the inductor are located on opposing sides of the first die comprising the first, second, and third TSVs.

12. The integrated circuit structure of claim 10, further comprising:

a fourth TSV comprising a first end and a second end; and

a second bottom formed of a third conductive material configured to couple the second end of the third TSV with the second end of the fourth TSV.

13. The integrated circuit structure of claim 12, wherein an input node of the inductor and an output node of the inductor are located on a same side of the first die comprising the first, second, third, and fourth TSVs.

14. The integrated circuit structure of claim 10, wherein:

the top is formed using a metallization layer of the die within which the first, second, and third TSVs are implemented; and

the first bottom is formed using a metallization layer of a second die mounted to the first die, wherein the second die is the different die.

15. The integrated circuit structure of claim 10, wherein:

the first bottom is formed using a metallization layer of the first die within which the first, second, and third TSVs are implemented; and

the top is formed using a metallization layer of a second die mounted to the first die, wherein the second die is the different die.

16. The integrated circuit structure of claim 10, wherein:

the first, second, and third TSVs are implemented within the first die;

the first bottom is formed using a metallization layer of a second die coupled to the first die, wherein the second die is the different die; and

the top is formed using a metallization layer of a third die coupled to the first die.

18. The integrated circuit structure of claim 16, wherein:

the metallization layer forming the first bottom is within the second die; and

the metallization layer forming the top is within the third die.