Semiconductor devices including superlattice depletion layer stack and related methods

• US 9,406,753 B2
• Filed: 11/21/2014
• Issued: 08/02/2016
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert, Takeuchi, Hideki, Trautmann, Erwin
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Gauthier, Steven B
• Application Number:
  US14/550,272
• Publication Number:
  US 20150144878A1
• Time in Patent Office: 620 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.

Claims

1. A method for making a semiconductor device comprising:

forming an alternating stack of a plurality of superlattices and a plurality of bulk semiconductor layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

doping bulk semiconductor layers between respective superlattices with alternating dopant conductivity types defining a p-n junction;

forming spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattices and bulk semiconductor layers; and

forming a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;

wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

2. The method of claim 1 further comprising forming at least one shallow trench isolation (STI) region extending through the alternating stack of superlattice and bulk semiconductor layers and into the substrate.

3. The method of claim 1 wherein each base semiconductor portion comprises silicon.

4. The method of claim 1 wherein each base semiconductor portion comprises germanium.

5. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

6. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

7. The method of claim 1 wherein forming the gate comprises forming an oxide layer on the upper bulk semiconductor layer between the spaced apart source and drain regions, and forming a gate electrode overlying the oxide layer.

8. The method of claim 1 wherein less than half of the possible sites available for non-semiconductor atoms in each non-semiconductor monolayer to bond with semiconductor atoms from adjacent base semiconductor monolayers are occupied by non-semiconductor atoms.

19. The method of claim 1 wherein the channel is partially depleted.

20. The method of claim 1 wherein the channel is fully depleted.

9. A semiconductor device comprising:

an alternating stack of a plurality of superlattices and a plurality of bulk semiconductor layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, the bulk semiconductor layers between respective superlattices being doped with alternating dopant conductivity types defining a p-n junction;

spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattices and bulk semiconductor layers; and

a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;

wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

10. The semiconductor device of claim 9 further comprising at least one shallow trench isolation (STI) region extending through the alternating stack of superlattice and bulk semiconductor layers and into the substrate.

11. The semiconductor device of claim 9 wherein each base semiconductor portion comprises silicon.

12. The semiconductor device of claim 9 wherein each base semiconductor portion comprises germanium.

13. The semiconductor device of claim 9 wherein the at least one non-semiconductor monolayer comprises oxygen.

14. The semiconductor device of claim 9 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

15. The semiconductor device of claim 9 wherein the gate comprises an oxide layer on the upper bulk semiconductor layer between the spaced apart source and drain regions, and a gate electrode overlying the oxide layer.

16. The semiconductor device of claim 9 wherein less than half of the possible sites available for non-semiconductor atoms in each non-semiconductor monolayer to bond with semiconductor atoms from adjacent base semiconductor monolayers are occupied by non-semiconductor atoms.

21. The semiconductor device of claim 9 wherein the channel is partially depleted.

22. The semiconductor device of claim 9 wherein the channel is fully depleted.

17. A semiconductor device comprising:

an alternating stack of a plurality of superlattices and a plurality of bulk silicon layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, the bulk semiconductor layers between respective superlattices being doped with alternating dopant conductivity types defining a p-n junction;

spaced apart source and drain regions in an upper bulk silicon layer of the alternating stack of superlattices and bulk silicon layers; and

a gate on the upper bulk silicon layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;

wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

18. The semiconductor device of claim 17 further comprising at least one shallow trench isolation (STI) region extending through the alternating stack of superlattices and bulk silicon layers and into the substrate.