Semiconductor device and method of manufacturing semiconductor device

• US 9,406,757 B2
• Filed: 09/23/2014
• Issued: 08/02/2016
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US14/493,715
• Publication Number:
  US 20150194492A1
• Time in Patent Office: 679 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Claims

1. A semiconductor device comprising:

a semiconductor layer made of SiC;

a source region formed in the semiconductor layer, the source region forming a surface of the semiconductor layer;

a body region formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench dug down in the semiconductor layer from the surface thereof, the gate trench passing through the source region and the body region and the deepest portion thereof reaching the drain region;

a gate insulating film formed on an inner surface of the gate trench, the gate insulating film having a bottom portion located on the bottom surface thereof and a side portion located on the side surface thereof, the thickness of the bottom portion and the thickness of the side portion being different from each other;

a gate electrode embedded in the gate trench on the gate insulating film;

a source wiring formed on the semiconductor layer and in contact with the source region, the source wiring having a laminating structure a first source layer formed on the semiconductor layer and a second source layer formed on the first source layer, the first source layer and the second source layer made of conductive materials different from each other; and

a source trench dug down in the semiconductor layer from the surface thereof, wherein

the first source layer is conformal to a side surface and a bottom surface of the source trench,

wherein the source wiring selectively forms a first junction with respect to the semiconductor layer, the first junction having a smaller junction barrier than the diffusion potential of a body diode intrinsic in the semiconductor device.

2. The semiconductor device according to claim 1, wherein a non-ohmic contact is selectively formed between the source wiring and the semiconductor layer.

3. The semiconductor device according to claim 1, wherein the gate trench and the source trench have the same depth.

4. The semiconductor device according to claim 2, wherein the source trench is deeper than the gate trench.

5. The semiconductor device according to claim 2, wherein

the source region is an n⁺-type source region,

the drain region is an n-type drain region, and

the body region has a p-type region forming the side surface of the gate trench, and a p⁺-type region forming the side surface of the source trench and having an impurity concentration larger than that of the p-type region.

6. The semiconductor device according to claim 5, wherein an ohmic contact is selectively formed between the source wiring and the n⁺-type source region.

7. The semiconductor device according to claim 1, wherein the gate trench is formed to surround the source trench in plan view.

8. The semiconductor device according to claim 1, wherein the gate insulating film is a silicon oxynitride film formed by thermal oxidation with nitrogen-containing gas and the nitrogen content in the gate insulating film is 0.1 to 10%.

9. The semiconductor device according to claim 1, wherein the thickness of the bottom portion of the gate insulating film is 150 to 500 Å

.

10. The semiconductor device according to claim 1, wherein the thickness of the side portion of the gate insulating film is 300 to 1000 Å

.