Wafer level packaging of electronic devices

• US 9,406,854 B2
• Filed: 03/20/2012
• Issued: 08/02/2016
• Est. Priority Date: 09/20/2009
• Status: Active Grant

• Current Assignee: LED Wafer Solutions LLC
• Original Assignee: Mordehai Margalit
• Inventors: Margalit, Mordehai, Petronius, Israel
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/424,875
• Publication Number:
  US 20120261697A1
• Time in Patent Office: 1,596 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/483 Containers
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

Claims

1. A method of forming an electronic device package, the method comprising:

providing an electronic device comprising a first contact point disposed in a first hole defined in the electronic device, the first hole extending from a face of the electronic device;

depositing a metal pad on said first contact point to provide direct electrical connection to said first contact point;

providing a substrate comprising a first face and a second face opposing the first face of said substrate;

attaching said provided electronic device to said provided substrate, such that the first face of said provided substrate is adjacent the face of said provided electronic device;

after attaching said provided electronic device to said provided substrate, etching a vertical interconnect access (VIA) from said second face of said substrate and terminating at and in direct physical contact with said metal pad with no intervening layers there between, said VIA aligned with and comprising the first hole in the electronic device, said VIA including a first sidewall and a second sidewall;

applying an electrically insulating first passivation layer to said second face of said substrate, said electrically insulating first passivation layer conforming to an exposed surface of said etched via;

etching a contact hole through said electrically insulating first passivation layer at an apex of said etched via to at least contact said deposited metal pad; and

depositing a metal layer on the electrically insulating first passivation layer said metal layer including a first portion that substantially conforms to a first exposed surface of said first sidewall, a second portion that substantially conforms to a second exposed surface of said second sidewall, a third portion in direct physical contact with said deposited metal pad and said first and second portions of the metal layer, a fourth portion disposed above the second face of the substrate and integrally connected to the first portion of the metal layer, and a fifth portion disposed above the second face of the substrate and integrally connected to the second portion of the metal layer, wherein said first and second portions of said metal layer define a second hole there between, and said first portion, said second portion, said third portion, said fourth portion, and said fifth portion of said metal layer comprise a continuous metal layer.

2. The method of claim 1, wherein said applied electrically insulating first passivation layer is constituted of a polymer.

3. The method of claim 1, further comprising applying a second passivation layer in said second hole to at least partially contact said deposited metal layer, said passivation layer substantially conforming to said first and second portions of said metal layer.

4. The method of claim 3, wherein said second passivation layer is constituted of solder mask material.

5. The method of claim 1, wherein said substrate is constituted of silicon.

6. The method of claim 1, wherein said drilling extends through said deposited metal pad.

7. The method of any of claim 1, wherein said electronic device is constituted of a light emitting diode.

8. The method according to claim 1, wherein said provided electronic device comprises a second contact point electrically different from said first contact point and said attached substrate is constituted of a conductive material, and the method further comprises depositing a second metal pad in contact with the second contact point.

9. The method according to claim 1, further comprising:

providing a spacer element; and

affixing said provided spacer element to said provided substrate, said spacer element defining a location for said attaching of said provided electronic device to said provided substrate.

10. The method according to claim 9, wherein said provided spacer element is constituted of a reflective polymer.

11. The method according to claim 1, further comprising:

providing an optically transparent cover; and

affixing said provided optically transparent cover such that said provided electronic device is disposed between said provided substrate and said provided optically transparent cover.

12. The method according to claim 11, wherein said provided optically transparent cover comprises at least one of:

a lens;

a diffusing element;

a phosphor coating;

a color changing material coating;

an anti-reflective coating; and

an optical filter.

13. The method according to claim 11, further comprising:

providing a spacer element, wherein said provided spacer element defines a location for said affixing of said provided optically transparent cover.

14. The method according to claim 1, further comprising:

depositing a second metal pad on a second contact point of said electronic device to provide direct electrical connection to said second contact point, wherein said second contact point disposed on the face of the electronic device.

15. The method according to claim 14, further comprising:

etching a second contact hole through a portion of said electrically insulating first passivation layer to partially expose said second face of said substrate;

depositing a sixth portion of said metal layer in said second contact hole, said sixth portion in direct physical contact with said partially-exposed second face of said substrate, wherein said first portion, said second portion, said third portion, said fourth portion, said fifth portion, and said sixth portion of said metal layer comprise a continuous metal layer; and

defining a metal gap in said fifth portion of said metal layer to electrically isolate said first, second, third, and fourth portions of said metal layer from said sixth portion of said metal layer, thereby electrically isolating said first contact from said second contact.