System for isolating integrated circuit power domains

• US 9,407,264 B1
• Filed: 05/17/2015
• Issued: 08/02/2016
• Est. Priority Date: 05/17/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ali, Inayat, Sharma, Parul
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US14/714,333
• Time in Patent Office: 443 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A system for isolating a first power domain from a second power domain in an integrated circuit includes receiving an input signal from the first power domain and receiving a set of bits from a programmable register. An isolation enable signal indicative of isolating the first power domain from the second power domain is generated, and an intermediate signal based on the isolation enable signal and the input signal is generated. At least one of the input signal, a logic low signal, a logic high signal, and the intermediate signal is output based on the isolation enable signal and the set of bits.

Claims

1. A system for isolating a first power domain of an integrated circuit (IC) from a second power domain of the IC, the system comprising:

a first multiplexer having a first two-bit input terminal for receiving first and second bit signals, a second two-bit input terminal for receiving third and fourth bit signals, a select terminal for receiving an isolation enable signal, and a two-bit output terminal for outputting fifth and sixth bit signals; and

an isolation circuit, comprising;

a logic gate connected to the two-bit output terminal of the first multiplexer for receiving the fifth and sixth bit signals, and for generating an enable signal;

a latch having a first input terminal for receiving an input signal, an enable terminal connected to the logic gate for receiving the enable signal, and an output terminal for outputting a latched signal; and

a second multiplexer having a first input terminal for receiving the input signal, a second input terminal for receiving a logic low signal, a third input terminal for receiving a logic high signal, a fourth input terminal connected to the latch for receiving the latched signal, a two-bit select terminal connected to the first multiplexer for receiving the fifth and sixth bit signals, and an output terminal for outputting an isolation signal,

wherein the isolation circuit is configurable for outputting at least one of the input signal, the logic low signal, the logic high signal, and the latched signal as the isolation signal for isolating the first power domain from the second power domain based on the fifth and sixth bit signals.

2. The system of claim 1, wherein the fifth and sixth bit signals are at logic low states when the isolation enable signal is at a logic low state and the third and fourth bit signals are at logic low states.

3. The system of claim 2, wherein the isolation circuit outputs the isolation signal as the input signal when the fifth and sixth bit signals are at logic low states.

4. The system of claim 1, wherein:

the fifth and sixth bit signals are at logic low and logic high states, respectively, when the isolation enable signal is high and the first and second bit signals are at logic low and logic high states, respectively,

the fifth and sixth bit signals are at logic high and logic low states, respectively, when the isolation enable signal is high and the first and second bit signals are at logic high and logic low states, respectively, and

the fifth and sixth bit signals are at logic high states when the isolation enable signal is high and the first and second bit signals are high.

5. The system of claim 4, wherein:

the isolation circuit outputs the logic low signal as the isolation signal when the fifth and sixth bit signals are at logic low and logic high states, respectively, and

the isolation circuit provides the logic low signal to the second power domain for isolating the first power domain from the second power domain.

6. The system of claim 4, wherein:

the isolation circuit outputs the logic high signal as the isolation signal when the fifth and sixth bit signals are at logic high and logic low states, respectively, and

the isolation circuit provides the logic high signal to the second power domain for isolating the first power domain from the second power domain.

7. The system of claim 4, wherein:

the isolation circuit outputs the latched signal as the isolation signal when the fifth and sixth bit signals are high, and

the isolation circuit provides the latched signal to the second power domain for isolating the first power domain from the second power domain.

8. The system of claim 1, further comprising a programmable register for storing first and second bits, and outputting the first and second bit signals corresponding to the first and second bits, respectively, wherein the first and second bits are configurable for selecting an isolation type of the isolation circuit.

9. The system of claim 8, further comprising a power gating control circuit for generating the isolation enable signal.

10. The system of claim 9, wherein the power gating control circuit, the programmable register, and the first multiplexer form a power gating controller.

11. The system of claim 1, wherein the first and second bit signals are configurable by at least one of a configuration circuit, an external pin, and an electrically programmable fuse.

12. A system for isolating a first power domain of an integrated circuit from a second power domain of the integrated circuit, wherein the first power domain outputs an input signal, the system comprising:

a power gating control circuit for generating an isolation enable signal; and

a multiplexer having a first input terminal for receiving a first bit signal that is configurable for selecting an isolation type, a second input terminal connected to the first power domain for receiving the input signal, a select terminal connected to the power gating control circuit for receiving the isolation enable signal, and an output terminal for outputting at least one of the input signal and the first bit signal as an isolation signal,

wherein the multiplexer isolates the first power domain from the second power domain when the isolation enable signal is at a logic high state.

13. The system of claim 12, wherein:

the multiplexer provides a logic high signal as the isolation signal to the second power domain for isolating the first power domain from the second power domain when the first bit signal is high and the isolation enable signal is high, and

the multiplexer provides a logic low signal as the isolation signal to the second power domain for isolating the first power domain from the second power domain when the first bit signal is low and the isolation enable signal is high.

14. The system of claim 12, further comprising a programmable register for storing a first bit and outputting the first bit signal corresponding to the first bit, wherein the first bit is configurable, and wherein the power gating control circuit and the programmable register form a power gating controller.

15. The system of claim 12, wherein the first bit signal is configurable by at least one of a configuration circuit, an external pin, and an electrically programmable fuse.

16. A method for isolating a first power domain of an integrated circuit from a second power domain of the integrated circuit using an isolation circuit and a power gating control circuit, the method comprising:

receiving an input signal from the first power domain;

receiving a set of bit signals for selecting an isolation type of the isolation circuit, wherein the isolation circuit is configurable as first and second isolation types based on the set of bit signals and an isolation enable signal;

receiving the isolation enable signal from the power gating control circuit, wherein the isolation enable signal is indicative of isolating the first power domain from the second power domain;

generating an intermediate signal based on the input signal and the isolation enable signal;

outputting the input signal to the second power domain when the isolation enable signal is disabled; and

outputting at least one of a logic high signal, a logic low signal, and the intermediate signal to the second power domain based on the set of bit signals when the isolation enable signal is enabled.

17. The method of claim 16, wherein the logic low signal is provided to the second power domain when the isolation circuit is configured as the first isolation type, and wherein the logic high signal is provided to the second power domain when the isolation circuit is configured as the second isolation type, thereby isolating the first power domain from the second power domain.

18. The method of claim 17, wherein the intermediate signal is provided to the second power domain when the isolation circuit is configured as a third isolation type, thereby isolating the first power domain from the second power domain.

19. The method of claim 17, wherein the intermediate signal is generated by a latch that receives the input signal and the isolation enable signal, wherein a value of the input signal is latched and output as the intermediate signal when the isolation enable signal is enabled, and wherein the value of the intermediate signal is retained until the isolation enable signal is disabled.

20. The method of claim 17, wherein the set of bit signals are configurable by at least one of a configuration circuit, an external pin, an electrically programmable fuse, and a set of bits corresponding to the set of bit signals stored in a programmable register.