Systems and methods for distributing an aging burden among processor cores

• US 9,407,272 B2
• Filed: 12/30/2011
• Issued: 08/02/2016
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Penzes, Paul, Fullerton, Mark, Jung, Hwisung, Walley, John, Sippel, Tim, Kothari, Love
• Primary Examiner(s): Wai, Eric C
• Assistant Examiner(s): Lee, James J
• Application Number:
  US13/341,748
• Publication Number:
  US 20130047166A1
• Time in Patent Office: 1,677 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Claims

1. A system for distributing aging burden among a plurality of processor cores comprising:

a processor including the plurality of processor cores comprised of semiconductor material; and

a Power Management Unit (PMU) coupled to the processor, wherein the PMU is configured to;

track, using a plurality of different types of aging mechanisms, aging of the respective semiconductor material of the processor cores, wherein the aging mechanisms include detection of slowed frequency performance, threshold voltage variation, and substrate current level of the respective processor cores,

monitor, based on the tracked plurality of different types of aging mechanisms, a difference in aging of the respective semiconductor material during respective lifetimes of the plurality of processor cores,

determine whether the difference in aging between the respective semiconductor material of a first processor core of the plurality of processor cores and a second processor core of the plurality of processor cores has exceeded a predetermined threshold, and

reassign, in response to determining that the difference in aging has exceeded the predetermined threshold, an instruction assigned to the first processor core of the plurality of processor cores to the second processor core of the plurality of processor cores for execution if the respective semiconductor material of the first processor core of the plurality of processor cores has aged more than the respective semiconductor material of the second processor core of the plurality of processor cores.

2. The system of claim 1, wherein the PMU is further configured to:

reassign, in response to determining that the difference in aging has exceeded the predetermined threshold, an instruction assigned to the second processor core of the plurality of processor cores to the first processor core of the plurality of processor cores for execution if the respective semiconductor material of the second processor core of the plurality of processor cores has aged more than the respective semiconductor material of the first processor core of the plurality of processor cores.

3. The system of claim 1, wherein the PMU is further configured to:

monitor loads on the plurality of processor cores;

predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and

pre-charge the first processor core of the plurality of processor cores responsive to predicting the increased load.

4. The system of claim 1, wherein the PMU is further configured to:

monitor loads on the plurality of processor cores;

predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and

reduce a processing frequency of the first processor core of the plurality of processor cores responsive to predicting the increased load.

5. The system of claim 1, wherein the PMU is further configured to:

monitor temperature of the plurality of processor cores;

determine whether a temperature of the first processor core of the plurality of processor cores has exceeded a temperature threshold; and

select a cooler processor core of the plurality of processor cores for execution of an instruction assigned to the first processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold.

6. The system of claim 1, wherein the PMU is further configured to:

monitor temperature of the plurality of processor cores, wherein the first processor core of the plurality of processor cores is configured to process a first thread of a multi-threaded application, and wherein a second processor core of the plurality of processor cores is configured to process a second thread of the multi-threaded application;

determine whether a temperature of the first processor core of the plurality of processor cores has exceeded a temperature threshold;

determine whether a cooler processor core of the plurality of processor cores is available to process the first thread; and

process the first thread using the cooler processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold and that the cooler processor core of the plurality of processor cores is available to process the first thread.

7. The system of claim 6, wherein the PMU is further configured to:

process the first thread and the second thread using the second processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold and that no cooler processor core of the plurality of processor cores other than the second processor core of the plurality of processor cores is available to process the first thread.

8. The system of claim 1, wherein the PMU is further configured to:

determine a relative difference in aging among the plurality of processor cores; and

assign, based on the determined relative difference in aging, power states to the plurality of processor cores.

9. The system of claim 1, wherein the PMU is further configured to:

determine a relative difference in temperature among the plurality of processor cores; and

assign, based on the determined relative difference in temperature, power states to the plurality of processor cores.

10. A system for distributing aging burden among a plurality of processor cores comprising:

a processor including the plurality of processor cores; and

a Power Management Unit (PMU) coupled to the processor, wherein the PMU is configured to;

track aging of the plurality of processor cores based on changes in device characteristics of the respective plurality of processor cores, wherein the changes in device characteristics comprise slowed frequency performance, threshold voltage variation, and substrate current level in the respective processor cores,

monitor a difference in aging among the plurality of processor cores,

rotate execution of an application among the plurality of processor cores based on a predetermined aging scheme such that;

the plurality of processor cores age approximately evenly over respective lifetimes of the plurality of processor cores,

the difference in aging among the plurality of processor cores does not exceed a predetermined aging threshold, and

the execution of the application is transferred from a first processor core of the plurality of processor cores to a second processor core of the plurality of processor cores in response to determining that a first aging threshold corresponding to the first processor core of the plurality of processor cores has been reached and the second processor core of the plurality of processor cores has aged less than the first processor core of the plurality of processor cores.

11. The system of claim 10, wherein the PMU is further configured to execute the application on the first processor core of the plurality of processor cores and the second processor core of the plurality of processor cores in parallel to determine whether the first aging threshold of the first processor core of the plurality of processor cores has been reached.

12. The system of claim 10, wherein the PMU is further configured to:

determine a relative difference in temperature of the plurality of processor cores;

assign a first power state to the first processor core of the plurality of processor cores responsive to determining that the first processor core of the plurality of processor cores is below a first temperature threshold; and

assign a second power state to the first processor core of the plurality of processor cores responsive to determining that the first processor core of the plurality of processor cores is above the first temperature threshold.

13. The system of claim 12, wherein the PMU is further configured to:

assign the second power state to the first processor core of the plurality of processor cores responsive to determining that the first processor core of the plurality of processor cores is above the first temperature threshold but below a second temperature threshold; and

assign a third power state to the first processor core of the plurality of processor cores responsive to determining that the first processor core of the plurality of processor cores is above the second temperature threshold.

14. The system of claim 10, wherein the PMU is further configured to:

monitor loads on the plurality of processor cores;

predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and

pre-charge the first processor core of the plurality of processor cores responsive to predicting the increased load.

15. The system of claim 10, wherein the PMU is further configured to:

monitor loads on the plurality of processor cores;

predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and

reduce a processing frequency of the first processor core of the plurality of processor cores responsive to predicting the increased load.

16. The system of claim 10, wherein the PMU is further configured to:

monitor temperatures of the plurality of processor cores;

determine whether a temperature of the first processor core of the plurality of processor cores has exceeded a temperature threshold; and

select a cooler processor core of the plurality of processor cores for execution of the application assigned to the first processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold.

17. A system for distributing aging burden among a plurality of processor cores comprising:

a first processor core;

a second processor core; and

a Power Management Unit (PMU) coupled to the first processor core and the second processor core, wherein the PMU is configured to;

monitor changes in device characteristics of the first processor core and the second processor core, wherein the changes in device characteristics comprise slowed frequency performance, threshold voltage variation, and substrate current level in the respective processor cores,

determine, based on the monitored changes in device characteristics, whether semiconductor material of the first processor core has aged faster than semiconductor material of the second processor core so that a difference in aging between the semiconductor material of the first processor core and the semiconductor material of the second processor core has exceeded a predetermined aging threshold, and

reassign, in response to determining that the difference in aging has exceeded the predetermined aging threshold, an instruction assigned to the first processor core to the second processor core for execution if the semiconductor material of the first processor core has aged more than the semiconductor material of the second processor core.

18. The system of claim 17, wherein the PMU is further configured to monitor bias temperature instability of the first processor core and the second processor core.

19. The system of claim 17, wherein the PMU is further configured to monitor substrate current levels of the first processor core and the second processor core, wherein the monitored substrate current levels indicate hot carrier injection (HCI) in the first processor core and the second processor core.

20. The system of claim 17, wherein the PMU is further configured to monitor channel current levels of the first processor core and the second processor core.