System and method using cascaded single partity check coding
First Claim
Patent Images
1. A system comprising:
- a parity bit encoder configured to encode successive blocks of n−
3 bits with three parity bits to provide successive blocks of n bits;
a Gray mapper coupled to said parity bit encoder and configured to map each one of said blocks of n bits to three associated quadrature amplitude modulated (QAM) symbols;
a modulator coupled to said Gray mapper and configured to modulate an optical signal in response to an output of said Gray mapper to provide a modulated optical signal comprising said three associated QAM symbols;
a detector for receiving said modulated optical signal and providing an electrical signal representative of said optical signal; and
a de-mapper configured to provide a de-mapper output representative of said blocks of n−
3 bits in response to said electrical signal.
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Abstract
A system and method including a parity bit encoder for encoding each n−3 bits of data to be transmitted with three parity check bits to produce blocks of n bits (n−3 information bits plus three parity bits associated with the n information bits). Each of the blocks of n bits are Gray mapped to three QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A maximum a posteriori (MAP) decoder is used at the receiver to correct for cycle slip.
53 Citations
20 Claims
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1. A system comprising:
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a parity bit encoder configured to encode successive blocks of n−
3 bits with three parity bits to provide successive blocks of n bits;a Gray mapper coupled to said parity bit encoder and configured to map each one of said blocks of n bits to three associated quadrature amplitude modulated (QAM) symbols; a modulator coupled to said Gray mapper and configured to modulate an optical signal in response to an output of said Gray mapper to provide a modulated optical signal comprising said three associated QAM symbols; a detector for receiving said modulated optical signal and providing an electrical signal representative of said optical signal; and a de-mapper configured to provide a de-mapper output representative of said blocks of n−
3 bits in response to said electrical signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An optical signal receiver comprising:
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a detector for receiving a modulated optical signal representing blocks of n bits comprising n−
3 information bits and three parity bits mapped to three associated quadrature amplitude modulated (QAM) signals and for providing an electrical signal representative of said optical signal; anda de-mapper configured to provide a de-mapper output representative of said n−
3 information bits in response to said electrical signal. - View Dependent Claims (10, 11, 12, 13)
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14. A method comprising:
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encoding successive blocks of n−
3 bits of a signal with three parity bits to provide successive blocks of n bits;Gray mapping said successive blocks of n bits to three associated quadrature amplitude modulated (QAM) symbols; modulating said three associated QAM symbols on an optical carrier wavelength to provide a modulated optical signal; detecting said modulated optical signal to provide an electrical signal; and de-mapping said three associated QAM symbols from said electrical signal to provide a de-mapper output representative of said blocks of n−
3 bits. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification