Methods and arrangements to decode communications

• US 9,407,732 B2
• Filed: 11/26/2012
• Issued: 08/02/2016
• Est. Priority Date: 11/26/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Azizi, Shahrnaz, Perahia, Eldad, Kenney, Thomas J., Park, Minyoung
• Primary Examiner(s): Mattis, Jason
• Assistant Examiner(s): Shao, Hong
• Application Number:
  US13/685,631
• Publication Number:
  US 20140146722A1
• Time in Patent Office: 1,345 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

Embodiments may comprise logic such as hardware and/or code to reduce power consumption by, e.g., a device such as a station or relay by implementing prediction logic to decode and determine whether a communication affects the operation of the device. Some embodiments may comprise logic to receive at least a portion of a header of a frame from a physical layer and begin to decode the portion of the header of the frame without first checking the correctness of the value in the frame check sequence field. In many embodiments, prediction logic may determine whether the frame could have an impact on the operation of the device. For circumstances in which the prediction logic determines that the frame will not have an impact, the MAC logic may terminate processing, receipt, and decoding of the frame and enter the device into a low power consumption state.

Claims

1. A method to decode communications by a device, the method comprising:

receiving at least a portion of a header of a frame;

examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame, wherein examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examining frame type and subtype values to determine if the frame comprises a network allocation vector;

determining that the at least a portion of header of the frame does not impact operation of the device, based upon the examining; and

disregarding processing of a remaining portion of the frame and entering a power save mode.

2. The method of claim 1, further comprising:

receiving at least a portion of a header of a second frame;

examining the at least a portion of the header of the second frame without processing a frame body of the second frame, or performing a cyclic redundancy check, of the second frame;

determining that the at least a portion of the header of the second frame might impact operation of the device, based upon the examining;

processing the remaining portion of the frame and performing the cyclic redundancy check of the second frame; and

parsing the second frame.

3. The method of claim 1, further comprising storing at least part of the frame in memory.

4. The method of claim 1, wherein receiving the at least a portion of the header of the frame comprises receiving from a physical layer, one or more addresses from the header of the frame.

5. The method of claim 1, wherein receiving the at least a portion of the header of the frame comprises receiving from a physical layer, field values from the header of the frame as the at least a portion of the header of the frame is decoded.

6. The method of claim 1, wherein receiving the at least a portion of the header of the frame comprises receiving from a physical layer, frame type and subtype field values from the header of the frame.

7. The method of claim 1, wherein examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examining the at least a portion of the header of the frame before the frame check sequence field value is decoded by the physical layer.

8. The method of claim 1, wherein examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises comparing one or more addresses from the header of the frame against addresses previously associated with the device.

9. An apparatus to decode communications, the apparatus comprising:

medium access control logic to receive at least a portion of a header of a frame;

examine the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame, wherein examination of the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examination of frame type and subtype values to determine if the frame comprises a network allocation vector;

determine that the at least a portion of the header of the frame does not impact operation of the medium access control logic, based upon examining the at least a portion of the header of the frame; and

disregard processing of a remaining portion of the frame and enter a power save mode; and

a physical layer coupled with the medium access control logic to receive and decode the at least a portion of the frame.

10. The apparatus of claim 9, further comprising memory to store at least part of the frame.

11. The apparatus of claim 9, wherein the medium access control logic comprises logic to receive at least a portion of a header of a second frame;

examine the at least a portion of the header of the second frame without processing a frame body of the second frame and without performing a cyclic redundancy check of the second frame;

determine that the at least a portion of the header of the second frame might impact operation of the medium access control logic, based upon examining the at least a portion of the header of the second frame;

process a remaining portion of the second frame and perform the cyclic redundancy check of the second frame; and

parse the second frame.

12. The apparatus of claim 9, wherein the medium access control logic comprises logic to receive from the physical layer, one or more addresses from the header of the frame.

13. The apparatus of claim 9, wherein the medium access control logic comprises logic to receive from the physical layer, field values from the header of the frame as the at least a portion of the header of the frame is decoded.

14. The apparatus of claim 9, wherein the medium access control logic comprises logic to receive from the physical layer, from the physical layer, frame type and subtype field values from the header of the frame.

15. The apparatus of claim 9, wherein the medium access control logic comprises logic to examine the at least a portion of the header of the frame before the frame check sequence field value is decoded by the physical layer.

16. The apparatus of claim 9, wherein the medium access control logic comprises logic to compare one or more addresses from the header of the frame against addresses previously associated with the medium access control logic.

17. The apparatus of claim 9, wherein the physical layer comprises logic to transmit one or more addresses of the header of the frame to the medium access control logic and to store frame type and subtype values in a buffer as the frame is being decoded.

18. A system to decode communications, the system comprising:

medium access control logic to receive at least a portion of a header of a frame;

examine the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame, wherein examination of the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examination of frame type and subtype values to determine if the frame comprises a network allocation vector;

determine that the at least a portion of the header of the frame does not impact operation of the medium access control logic, based upon examining the at least a portion of the header of the frame; and

disregard processing of a remaining portion of the frame and enter a power save mode;

a physical layer coupled with the medium access control logic to receive and decode the at least a portion of the frame; and

an antenna coupled with the physical layer logic to receive the frame.

19. The system of claim 18, further comprising memory to store at least part of the frame.

20. The system of claim 18, wherein the medium access control logic comprises logic to receive at least a portion of a header of a second frame;

examine the at least a portion of the header of the second frame without processing a frame body of the second frame and without performing a cyclic redundancy check of the second frame;

determine that the at least a portion of the header of the second frame might impact operation of the medium access control logic, based upon examining the at least a portion of the header of the second frame;

process a remaining portion of the second frame and perform the cyclic redundancy check of the second frame; and

parse the second frame.

21. The system of claim 18, wherein the medium access control logic comprises logic to receive from the physical layer, one or more addresses from the header of the frame.

22. The system of claim 18, wherein the medium access control logic comprises logic to receive from the physical layer, field values from the header of the frame as the at least a portion of the header of the frame is decoded.

23. The system of claim 18, wherein the medium access control logic comprises logic to receive from the physical layer, from the physical layer, frame type and subtype field values from the header of the frame.

24. The system of claim 18, wherein the medium access control logic comprises logic to examine the at least a portion of the header of the frame before the frame check sequence field value is decoded by the physical layer.

25. The system of claim 18, wherein the physical layer comprises logic to transmit one or more addresses of the header of the frame to the medium access control logic and to store frame type and subtype values in a buffer as the frame is being decoded.

26. A computer program product to decode communications, the computer program product comprising:

a non-transitory computer useable medium having a computer useable program code embodied therewith, the computer useable program code comprising computer useable program code configured to perform operations, the operations comprising;

receiving at least a portion of a header of a frame;

examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame, wherein examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examining frame type and subtype values to determine if the frame comprises a network allocation vector;

determining that the at least a portion of header of the frame does not impact operation of the medium access control sublayer logic, based upon the examining; and

disregarding processing of a remaining portion of the frame and entering a power save mode.

27. The computer program product of claim 26, further comprising:

receiving at least a portion of a header of a second frame;

examining the at least a portion of the header of the second frame without processing a frame body of the second frame, or performing a cyclic redundancy check, of the second frame;

determining that the at least a portion of the header of the second frame might impact operation of the medium access control sublayer logic, based upon the examining;

processing a remaining portion of the second frame and performing the cyclic redundancy check of the second frame; and

parsing the second frame.

28. The computer program product of claim 26, wherein examining the at least a portion of the header of the frame without performing a cyclic redundancy check of the frame comprises examining the at least a portion of the frame before the frame check sequence field value is decoded by the physical layer.