Method of constructing an implantable microelectrode array

• US 9,409,011 B2
• Filed: 06/30/2014
• Issued: 08/09/2016
• Est. Priority Date: 01/21/2011
• Status: Active Grant

• Current Assignee: California Institute of Technology, Regents of the University of California (University of California), University of Louisville
• Original Assignee: California Institute of Technology, Regents of the University of California (University of California), University of Louisville
• Inventors: Tai, Yu-Chong, Nandra, Mandheerej S., Burdick, Joel W., Rodger, Damien Craig, Fong, Andy, Edgerton, Victor Reggie, Roy, Roland R., Gerasimenko, Yury, Lavrov, Igor, Harkema, Susan J., Angeli, Claudia A.
• Primary Examiner(s): Arbes, Carl
• Application Number:
  US14/320,316
• Publication Number:
  US 20140316503A1
• Time in Patent Office: 771 Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/0553 Paddle shaped electrodes, e.g. for laminotomy
• CPC Class Codes: A61N 1/0558 Anchoring or fixation means therefor

Abstract

An implantable electrode array assembly configured to apply electrical stimulation to the spinal cord. A substantially electrically nonconductive layer of the device has a first portion positionable alongside the spinal cord that includes a plurality of first openings. The layer has a second portion that includes a plurality of second openings. Electrodes and traces are positioned inside a peripheral portion of a body portion of the device and alongside the layer. At least one of the first openings is adjacent each of the electrodes to provide a pathway through which the electrode may provide electrical stimulation to the spinal cord. At least one of the second openings is adjacent each of the traces to provide a pathway through which the trace may receive electrical stimulation. At least one trace is connected to each electrode and configured to conduct electrical stimulation received by the trace(s) to the electrode.

Claims

1. A method of constructing an implantable electrode array assembly, the method comprising:

applying electrically conductive material to a frame layer forming a patterned layer of electrically conductive material defining a plurality of electrodes and a plurality of traces, at least one trace being connected to each of the plurality of electrodes, wherein at least a portion of the electrically conductive material is applied to a sacrificial material, wherein the portion of the conductive material is removed with the sacrificial material;

forming a first layer of a substantially electrically nonconductive material, the first layer being adjacent the patterned layer;

forming a plurality of first openings in the first layer, the first openings providing access to the plurality of electrodes through the first layer, a different grid defining portion of the first openings being adjacent each of the electrodes, each grid defining portion exposing a plurality of contacts of the electrode to which the grid defining portion is adjacent; and

forming a plurality of second openings in the first layer, the second openings providing access to the plurality of traces through the first layer.

2. The method of claim 1, further comprising:

positioning a sacrificial layer on a substrate;

forming a second layer of a substantially electrically nonconductive material on the sacrificial layer;

the patterned layer being positioned on the second layer; and

removing the sacrificial layer to thereby release the second layer from the substrate.

3. The method of claim 2, further comprising:

forming the frame layer on the substrate, the frame layer being underneath the second layer, the frame layer at least partially defining a frame around the patterned layer.

4. The method of claim 2, wherein the first and second layers are each formed from at least one of parylene-A, parylene-C, parylene-AM, parylene-F, paryleneN, and parylene-D.

5. The method of claim 2, wherein the first and second layers are formed from the same material.

6. The method of claim 2, wherein the patterned layer is formed on the second layer using a metal deposition technology.

7. The method of claim 6, wherein the metal deposition technology is e-beam evaporation.

8. The method of claim 2, wherein the sacrificial layer comprises a photoresist material.

9. The method of claim 2, wherein the substrate is a silicon wafer.

10. The method of claim 2, further comprising:

applying a coating to at least a portion of the second layer and at least a portion of the first layer.

11. The method of claim 1, wherein the plurality of first openings are etched in the first layer.

12. The method of claim 1, wherein the plurality of second openings are etched in the first layer.