System and method for gyroscope zero-rate-offset drift reduction through demodulation phase error correction

• US 9,410,806 B2
• Filed: 08/26/2013
• Issued: 08/09/2016
• Est. Priority Date: 08/26/2013
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Ezekwe, Chinwuba D.
• Primary Examiner(s): Desta, Elias
• Application Number:
  US14/010,163
• Publication Number:
  US 20150057959A1
• Time in Patent Office: 1,079 Days
• US Class Current: 1/1
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719

Abstract

A circuit for processing signals from a gyroscope includes a first that generates an in-phase demodulated signal and a second demodulator that generates a quadrature-phase demodulated signal with reference to in-phase and quadrature-phase modulated signals, respectively, from the gyroscope. The circuit includes a digital processor that receives the demodulated in-phase and quadrature phase signals from the demodulators and generates an output signal corresponding to a rotation of the gyroscope along a predetermined axis with reference to the in-phase demodulated signal and the quadrature-phase demodulated signal to remove a portion of the quadrature-phase signal from the in-phase signal.

Claims

1. A circuit for processing signals from a gyroscope comprising:

a first demodulator configured to receive a modulated signal from an output of a sensing element in the gyroscope, the first demodulator generating an in-phase demodulated signal with reference to the modulated signal;

a second demodulator configured to receive the modulated signal from the output of the sensing element in the gyroscope, the second demodulator generating a quadrature-phase demodulated signal with reference to the modulated signal; and

a digital processor configured to receive the demodulated in-phase signal from an output of the first demodulator and the demodulated quadrature-phase signal from an output of the second demodulator, the digital processor being configured to;

generate an output signal corresponding to a rotation of the gyroscope along a predetermined axis with reference to the in-phase demodulated signal and the quadrature-phase demodulated signal to remove a portion of the quadrature-phase signal from the in-phase signal.

2. The circuit of claim 1, the digital processor being further configured to:

generate a scaled datum corresponding to a product of a datum of the quadrature-phase signal multiplied by a scaling factor to reduce an absolute value of the digital datum;

generate the output signal with another datum corresponding to a difference between a datum corresponding to the in-phase signal and the scaled datum.

3. The circuit of claim 2 further comprising:

a temperature sensor configured to generate a signal corresponding to a temperature of the gyroscope.

4. The circuit of claim 3, the temperature sensor further comprising:

a proportional to absolute temperature (PTAT) sensor element; and

an analog to digital converter (ADC) electrically connected to an output of the PTAT sensor element and configured to generate digital temperature data corresponding to the signal generated by the PTAT.

5. The circuit of claim 3 wherein the digital processor is operatively connected to an output of the temperature sensor and the digital processor is further configured to:

receive data corresponding to the temperature of the gyroscope from the temperature sensor;

adjust the scaling factor with reference to the temperature of the gyroscope; and

multiply the datum corresponding to the quadrature-phase signal by the adjusted scaling factor to reduce an absolute value of the digital datum corresponding to the quadrature-phase signal.

6. The circuit of claim 1 further comprising:

a phase lock loop circuit operatively connected to the first demodulator and the second demodulator, the phase lock loop being configured to;

receive a signal corresponding to motion of a drive axis in the gyroscope;

generate a first signal to control the first demodulator, the first signal being generated with a first phase at a predetermined frequency in response to the signal from the drive axis; and

generate a second signal with a second phase at the predetermined frequency to control the second demodulator, the second phase being different than the first phase.

7. The circuit of claim 6 wherein the second phase differs from the first phase by approximately π

/2 radians.

8. The circuit of claim 6 further comprising:

a capacitance to voltage converter electrically connected to an output of the drive axis in the gyroscope; and

the phase lock loop circuit being electrically connected to an output of the capacitance to voltage converter to enable the phase lock loop circuit to receive the signal from the drive axis in the gyroscope.

9. The circuit of claim 1 further comprising:

a capacitance to voltage converter electrically connected to the output of the sensing element in the gyroscope;

the first demodulator being electrically connected to an output of the capacitance to voltage converter to receive the modulated signal from the capacitance to voltage converter; and

the second demodulator being electrically connected to the output of the capacitance to voltage converter to receive the modulated signal from the capacitance to voltage converter.

10. The circuit of claim 1 further comprising:

a first ADC electrically connected to the output of the first demodulator and configured to generate digital data corresponding to the in-phase demodulated signal;

a second ADC electrically connected to the output of the second demodulator and configured to generate digital data corresponding to the quadrature-phase demodulated signal; and

the digital processor being connected to an output of the first ADC to receive the digital data corresponding to the in-phase demodulated signal and the digital processor being connected to an output of the second ADC to receive the digital data corresponding to the quadrature-phase demodulated signal.

11. The circuit of claim 10 wherein the first ADC and the second ADC are delta-sigma modulators.