Synchronization in a computing device

• US 9,411,363 B2
• Filed: 12/10/2014
• Issued: 08/09/2016
• Est. Priority Date: 12/10/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Keqiang, Lu, Jiwei, Lee, Yong-Fong
• Primary Examiner(s): Rampuria, Satish
• Application Number:
  US14/565,512
• Publication Number:
  US 20160170438A1
• Time in Patent Office: 608 Days
• Field of Search: 718101-108
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/825 the problem or solution involving locking
• CPC Class Codes: G06F 2201/865 Monitoring of software
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 8/52 Binary to binary
• CPC Class Codes: G06F 8/70 Software maintenance or management
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Claims

1. An apparatus comprising:

a processor to execute a process, the processor comprising at least one or more core(s);

a chipset;

a memory to store the process; and

logic to;

acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), wherein the performance monitoring data comprises at least one of processor utilization data and instructions retired data;

identify a spin loop associated with the process at least in part by identifying at least one of a detected hot function and/or a detected hot loop using the acquired performance monitoring data;

modify the identified spin loop using binary translation to create a modified process portion; and

implement redirection from the identified spin loop to the modified process portion.

2. The apparatus of claim 1, wherein the at least one of the detected hot function and/or the detected hot loop is identified based, at least in part, on one or more performance profile(s) related to the performance monitoring data.

3. The apparatus of claim 1, wherein the detected hot function has an associated function processor utilization parameter (PUP) greater than or equal to a function utilization threshold (UT) and a function instructions retired parameter (IRP) greater than or equal to a function instructions retired threshold (IRT), the detected hot loop has an associated loop PUP greater than or equal to a loop UT and a loop IRP greater than or equal to a loop IRT, and a number of instructions in the detected hot loop is less than or equal to an instruction threshold.

4. The apparatus of claim 3, wherein the function UT, the function IRT, the loop UT and the loop IRT are in the range of 20% to 100% and the instruction threshold is on the order of 100.

5. The apparatus of claim 1, wherein the logic is further to select one or more hot instructions for each of the detected hot function and the detected hot loop and each of the one or more selected hot instructions has at least one of a high instruction processor utilization parameter (PUP) and/or a high instruction instructions retired parameter (IRP) relative to other instructions in the detected hot function or the detected hot loop.

6. The apparatus of claim 1, wherein at least one of the identified spin loop comprises a pause instruction that has an associated pause instruction processor utilization parameter (PUP) greater than or equal to a pause instruction utilization threshold (UT) and an associated pause instruction instructions retired parameter (IRP) greater than or equal to a pause instruction instructions retired threshold (IRT) and/or the identified spin loop comprises a pause instruction and an atomic memory access instruction.

7. The apparatus of claim 1, wherein the modified process portion comprises at least one of a yield system call or an exponential back-off operation.

8. A method comprising:

executing, by a processor comprising one or more core(s), a process;

acquiring, by monitor thread logic, performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), wherein the performance monitoring data comprises at least one of processor utilization data and instructions retired data;

identifying, by kernel performance monitor driver logic, a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop;

modifying, by binary translator logic, the identified spin loop using binary translation to create a modified process portion; and

implementing, by the binary translator logic, redirection from the identified spin loop to the modified process portion.

9. The method of claim 8, further comprising detecting, by the kernel performance monitor driver logic, at least one of the detected hot function and/or the detected hot loop based, at least in part, on one or more performance profile(s) related to the performance monitoring data.

10. The method of claim 8, wherein the detected hot function has an associated function processor utilization parameter (PUP) greater than or equal to a function utilization threshold (UT) and a function instructions retired parameter (IRP) greater than or equal to a function instructions retired threshold (IRT), the detected hot loop has an associated loop PUP greater than or equal to a loop UT and a loop IRP greater than or equal to a loop IRT and a number of instructions in the detected hot loop is less than or equal to an instruction threshold.

11. The method of claim 10, wherein the function UT, the function IRT, the loop UT and the loop IRT are in the range of 20% to 100% and the instruction threshold is on the order of 100.

12. The method of claim 8, further comprising selecting, by kernel performance monitor driver logic, one or more hot instructions for each of the detected hot function and the detected hot loop, wherein each of the one or more selected hot instructions has at least one of a high instruction PUP and/or a high instruction IRP relative to other instructions in the detected hot function or the detected hot loop.

13. The method of claim 8, wherein at least one of the identified spin loop comprises a pause instruction that has an associated pause instruction processor utilization parameter (PUP) greater than or equal to a pause instruction utilization threshold (UT) and an associated pause instruction instructions retired parameter (IRP) greater than or equal to a pause instruction instructions retired threshold (IRT) and/or the identified spin loop comprises a pause instruction and an atomic memory access instruction.

14. The method of claim 8, wherein the modified process portion comprises at least one of a yield system call or an exponential back-off operation.

15. A computer-readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:

executing a process;

acquiring performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), wherein the performance monitoring data comprises at least one of processor utilization data and instructions retired data;

identifying a spin loop associated with the process, at least in part by identifying at least one of a detected hot function and/or a detected hot loop using the acquired performance monitoring data;

modifying the identified spin loop using binary translation to create a modified process portion; and

implementing redirection from the identified spin loop to the modified process portion.

16. The computer-readable storage device of claim 15, wherein identifying a spin loop associated with the process further comprises detecting at least one of the detected hot function and/or the detected hot loop based, at least in part, on one or more performance profile(s) related to the performance monitoring data.

17. The computer-readable storage device of claim 15, wherein the detected hot function has an associated function processor utilization parameter (PUP) greater than or equal to a function utilization threshold (UT) and a function instructions retired parameter (IRP) greater than or equal to a function instructions retired threshold (IRT), the detected hot loop has an associated loop PUP greater than or equal to a loop UT and a loop IRP greater than or equal to a loop IRT and a number of instructions in the detected hot loop is less than or equal to an instruction threshold.

18. The computer-readable storage device of claim 17, wherein the function UT, the function IRT, the loop UT and the loop IRT are in the range of 20% to 100% and the instruction threshold is on the order of 100.

19. The computer-readable storage device of claim 15, wherein the instructions that when executed by one or more processors results in the following additional operations comprising:

selecting one or more hot instructions for each of the detected hot function and the detected hot loop, each of the one or more selected hot instructions having at least one of a high instruction PUP and/or a high instruction IRP relative to other instructions in the detected hot function or the detected hot loop.

20. The computer-readable storage device of claim 15, wherein at least one of the identified spin loop comprises a pause instruction that has an associated pause instruction processor utilization parameter (PUP) greater than or equal to a pause instruction utilization threshold (UT) and an associated pause instruction instructions retired parameter (IRP) greater than or equal to a pause instruction instructions retired threshold (IRT) and/or the identified spin loop comprises a pause instruction and an atomic memory access instruction.

21. The computer-readable storage device of claim 15, wherein the modified process portion comprises at least one of a yield system call or an exponential back-off operation.