PHY based wake up from low power mode operation
First Claim
1. An apparatus comprising:
- a system on chip (SOC) integrated circuit comprising a first region having a processing core and a detector circuit and a second region electrically isolated from the first region and comprising an always on domain power island with a power control block, the power control block comprising an energy detector coupled to a host input line;
a first power supply module adapted to selectively apply power to the first region responsive to a main switch; and
a second power supply module adapted to continuously supply power to the second region, the power control block configured to open the main switch to enter a low power mode during which no electrical power is supplied to the first region, the power control block further configured to close the main switch to resume application of electrical power to the first region responsive to a detection of electrical energy on the host input line by the energy detector, the processing core operating in a fail on mode of operation responsive to the resumed application of electrical power to the first region to qualify the detection of electrical energy on the host input line by the energy detector as a wake up command using the detector circuit and status information supplied by the power control block and to transition to a normal operational mode to process host commands responsive to the qualification of the detection of the electrical energy as a wake up command, the status information comprising a status indication to the processing core indicative of a presence or an absence of a fault condition detected during the low power mode, the processing core initiating a cold boot reinitialization or a warm boot reinitialization responsive to the status indication from the power control block.
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Accused Products
Abstract
Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line.
56 Citations
20 Claims
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1. An apparatus comprising:
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a system on chip (SOC) integrated circuit comprising a first region having a processing core and a detector circuit and a second region electrically isolated from the first region and comprising an always on domain power island with a power control block, the power control block comprising an energy detector coupled to a host input line; a first power supply module adapted to selectively apply power to the first region responsive to a main switch; and a second power supply module adapted to continuously supply power to the second region, the power control block configured to open the main switch to enter a low power mode during which no electrical power is supplied to the first region, the power control block further configured to close the main switch to resume application of electrical power to the first region responsive to a detection of electrical energy on the host input line by the energy detector, the processing core operating in a fail on mode of operation responsive to the resumed application of electrical power to the first region to qualify the detection of electrical energy on the host input line by the energy detector as a wake up command using the detector circuit and status information supplied by the power control block and to transition to a normal operational mode to process host commands responsive to the qualification of the detection of the electrical energy as a wake up command, the status information comprising a status indication to the processing core indicative of a presence or an absence of a fault condition detected during the low power mode, the processing core initiating a cold boot reinitialization or a warm boot reinitialization responsive to the status indication from the power control block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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connecting a system on chip (SOC) integrated circuit to a power interface, the SOC comprising a first region and a second region electrically isolated from the first region as an always on domain power island, the first region having a processing core and a detector circuit, the second region having a power control block comprising an energy detector coupled to a host input line, the power interface comprising a first power supply module adapted to selectively apply first power to the first region and a second power supply module adapted to continuously supply second power to the second region, the second power supply module comprising a main switch between the first power supply module and a host input voltage terminal; opening the main switch to place the SOC into a low power mode by removing electrical power from the first region; closing the main switch to return electrical power to the first region responsive to a detection of electrical energy on the host input line by the energy detector to transition the processing core into a fail on mode of operation; using the processing core in the fail on mode of operation to qualify the detection of electrical energy on the host input line by the energy detector as a wake up command using the detector circuit and status information supplied by the power control block, the status information comprising a status indication to the processing core indicative of a presence or an absence of a fault condition detected during the low power mode; and using the processing core to transition the SOC to a normal operational mode to process host commands responsive to the qualification of the detection of the electrical energy as a wake up command by initiating a cold boot reinitialization or a warm boot reinitialization responsive to the status indication from the power control block. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification