High speed input/output performance in solid state devices
First Claim
1. A system, comprising:
- a memory buffer;
a plurality of flash memory interfaces, each flash memory interface being for communicating with a respective one or more of a plurality of flash memory devices; and
a memory controller, wherein the memory controller is operably connected to the memory buffer and the plurality of flash memory interfaces, the memory controller being configured to;
determine a plurality of data segments for transfer between the memory buffer and the plurality of flash memory devices via the plurality of flash memory interfaces;
associate the plurality of data segments with a plurality of respective memory commands;
allocate the plurality of memory commands among the plurality of flash memory interfaces, each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command;
transfer the plurality of data segments between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued, the data segments being transferred sequentially in an order corresponding to the queued memory commands.
7 Assignments
0 Petitions
Accused Products
Abstract
A method of transferring data in a flash storage device is provided. A plurality of data segments for transfer between a memory buffer and a plurality of flash memory devices via a plurality of flash memory interfaces is associated with a plurality of respective memory commands. The plurality of memory commands are allocated among the plurality of flash memory interfaces, with each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command. The plurality of data segments are transferred between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, with each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued. The data segments are transferred sequentially in an order corresponding to the queued memory commands.
28 Citations
20 Claims
-
1. A system, comprising:
-
a memory buffer; a plurality of flash memory interfaces, each flash memory interface being for communicating with a respective one or more of a plurality of flash memory devices; and a memory controller, wherein the memory controller is operably connected to the memory buffer and the plurality of flash memory interfaces, the memory controller being configured to; determine a plurality of data segments for transfer between the memory buffer and the plurality of flash memory devices via the plurality of flash memory interfaces; associate the plurality of data segments with a plurality of respective memory commands; allocate the plurality of memory commands among the plurality of flash memory interfaces, each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command; transfer the plurality of data segments between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued, the data segments being transferred sequentially in an order corresponding to the queued memory commands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer-implemented method, comprising:
-
determining a plurality of data segments for transfer between a memory buffer and a plurality of flash memory devices via a plurality of flash memory interfaces; associating the plurality of data segments with a plurality of respective memory commands; allocating the plurality of memory commands among the plurality of flash memory interfaces, each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command; and transferring the plurality of data segments between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued, the data segments being transferred sequentially in an order corresponding to the queued memory commands. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A storage device, comprising:
-
a volatile memory device; a plurality of flash memory devices; a plurality of flash memory interfaces, each flash memory interface communicatively connected to one or more of the plurality of flash memory devices; and a memory controller, wherein the memory controller is operably connected to the memory device and each of the plurality of flash memory interfaces, the memory controller being configured to; determine a plurality of data segments for transfer between the volatile memory device and the plurality of flash memory devices via the plurality of flash memory interfaces; associate the plurality of data segments with a plurality of respective memory commands; allocate the plurality data segments among the plurality of flash memory interfaces, each data segment being associated with a respective one of the memory commands queued at a respective one of the flash memory channels; and sequentially transfer the plurality of data segments between the volatile memory device and the plurality of flash memory devices, each respective data segment being transferred via the memory interface to which the respective data segment is allocated by the memory command associated with the data segment.
-
Specification