Method and system for work scheduling in a multi-chip system

• US 9,411,644 B2
• Filed: 03/07/2014
• Issued: 08/09/2016
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Kessler, Richard E., Snyder, Wilson P. II
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US14/201,541
• Publication Number:
  US 20150254104A1
• Time in Patent Office: 886 Days
• Field of Search: 257/723, 257/724, 257/777, 257/686, 370/412, 370/420, 370/423
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 2209/486 Scheduler internals
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5072 Grid computing

Abstract

According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.

Claims

1. A multi-chip system comprising:

multiple chip devices, at least one chip device of the multiple chip devices includes a work source component comprising a core processor or a coprocessor configured to create work items; and

one or more scheduler processors each associated with a corresponding chip device of the multiple chip devices, a scheduler processor of the one or more scheduler processors configured to assign a work item to a destination chip device of the multiple chip devices for processing upon receiving the work item from a work source component associated with a source chip device of the multiple chip devices.

2. The multi-chip system as recited in claim 1, wherein the work source component is configured to:

receive a pointer to a work entry; and

send the pointer to the work entry to the scheduler processor of the one or more scheduler processors.

3. The multi-chip system as recited in claim 1, wherein the work source component is configured to:

create a work entry; and

send a pointer associated with the work entry to the scheduler processor of the one or more scheduler processors.

4. The multi-chip system as recited in claim 1, wherein in assigning the work item to a chip device of the multiple chip devices, the scheduler processor is configured to assign the work item to a core processor of one or more core processors associated with the chip device.

5. The multi-chip system as recited in claim 1, wherein a single scheduler processor is configured to assign all work items from any work source component associated with a corresponding chip device, each work source component configured to send each corresponding work item to the single scheduler processor.

6. The multi-chip system as recited in claim 1, wherein the multi-chip system includes multiple scheduler processors configured to assign work items to chip devices, the work source component configured to select a scheduler processor of the multiple scheduler processors for scheduling a corresponding work item.

7. The multi-chip system as recited in claim 6, wherein in selecting a scheduler processor, the work source component is configured to select the same scheduler processor for scheduling work items associated with a common work flow.

8. The multi-chip system as recited in claim 6, wherein in assigning the work item to a chip device of the multiple chip devices, the scheduler processor is configured to assign the work item independently of other scheduler processors of the multiple scheduler processors.

9. The multi-chip system as recited in claim 1, wherein each scheduler processor includes multiple scheduling queues for scheduling work items and wherein the work source component is configured to select a scheduling queue for scheduling the work item.

10. The multi-chip system as recited in claim 9, wherein in selecting a scheduling queue, the work source component is further configured to maintain a list of scheduling queues associated with the one or more scheduler processors.

11. The multi-chip system as recited in claim 1, wherein in assigning a work item, the scheduler processor is configured to assign work items associated with a common work flow to the same first chip device.

12. The multi-chip system as recited in claim 1, wherein a work item includes a processing operation associated with a data packet.

13. The multi-chip system as recited in claim 1, wherein each chip device of the multiple chip devices includes a memory allocator configured to allocate memory for storing data associated with the work item in one of the multiple chip devices.

14. The multi-chip system as recited in claim 13, wherein in allocating memory, each memory allocator is further configured to allocate memory for storing the work item in the first chip device to which the work item is assigned.

15. The multi-chip system as recited in claim 13, wherein each memory allocator is further configured to maintain a list of buffers associated with the multiple chip devices for storing data associated with a work item.

16. The multi-chip system as recited in claim 1, wherein in assigning a work item to a destination chip device, a first scheduler processor residing in a first chip device is configured to forward the work item to a second scheduler processor located in the destination chip device, the destination chip device is different from the first chip device.

17. The multi-chip system as recited in claim 16, wherein forwarding the work item includes forwarding the work item through a communications channel designated to carry communications between coprocessors in the first chip device and coprocessors in the destination chip device.