Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select
First Claim
1. A method comprising:
- by program instructions on a computing device,receiving a first signal from a serial peripheral interface (‘
SPI’
) master, wherein the first signal is received by a first SPI peripheral directly coupled to the SPI master, and wherein the first SPI peripheral is operatively connected to a second SPI peripheral so that each peripheral is capable of servicing all instructions to the peripherals and only one peripheral executes each instruction;
receiving a second signal indicating whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral, the second signal comprising a polarity signal characterized by a threshold with a second signal value higher than the threshold indicating that the first SPI peripheral is a primary SPI peripheral and a second signal value lower than the threshold indicating that the first SPI peripheral is a backup SPI peripheral;
responsive to determining that the second signal indicates that the first SPI peripheral is the backup SPI peripheral, transmitting the first signal to the second SPI peripheral; and
responsive to determining that the second signal indicates that the first SPI peripheral is the primary SPI peripheral;
servicing an instruction contained in the first signal; and
transmitting a response signal to the second SPI peripheral.
3 Assignments
0 Petitions
Accused Products
Abstract
Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
18 Citations
16 Claims
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1. A method comprising:
by program instructions on a computing device, receiving a first signal from a serial peripheral interface (‘
SPI’
) master, wherein the first signal is received by a first SPI peripheral directly coupled to the SPI master, and wherein the first SPI peripheral is operatively connected to a second SPI peripheral so that each peripheral is capable of servicing all instructions to the peripherals and only one peripheral executes each instruction;receiving a second signal indicating whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral, the second signal comprising a polarity signal characterized by a threshold with a second signal value higher than the threshold indicating that the first SPI peripheral is a primary SPI peripheral and a second signal value lower than the threshold indicating that the first SPI peripheral is a backup SPI peripheral; responsive to determining that the second signal indicates that the first SPI peripheral is the backup SPI peripheral, transmitting the first signal to the second SPI peripheral; and responsive to determining that the second signal indicates that the first SPI peripheral is the primary SPI peripheral; servicing an instruction contained in the first signal; and transmitting a response signal to the second SPI peripheral. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus including a serial peripheral interface (‘
- SPI’
) master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is directly coupled to the second SPI peripheral so that each peripheral is capable of servicing all instructions to the peripherals and only one peripheral executes each instruction, wherein the first SPI peripheral carries out the steps of;receiving a first signal from the SPI master; receiving a second signal indicating whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral, the second signal comprising a polarity signal characterized by a threshold with a second signal value higher than the threshold indicating that the first SPI peripheral is a primary SPI peripheral and a second signal value lower than the threshold indicating that the first SPI peripheral is a backup SPI peripheral; responsive to determining that the second signal indicates that the first SPI peripheral is the backup SPI peripheral, transmitting the first signal to the second SPI peripheral; and responsive to determining that the second signal indicates that the first SPI peripheral is the primary SPI peripheral; servicing an instruction contained in the first signal; and transmitting, to the second SPI peripheral, a response signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
- SPI’
Specification