Low noise and low power passive sampling network for a switched-capacitor ADC with a slow reference generator
First Claim
1. A switched-capacitor integrator, comprising:
- an amplifier having first and second output nodes and first and second input nodes;
a first integration capacitor coupled between the first output node and the first input node;
a second integration capacitor coupled between the second output node and the second input node;
first and second sampling capacitors, each having a first terminal and a second terminal;
a first set of switches configured toconnect reference voltage nodes with the first terminals of the first and second sampling capacitors during a sampling phase of the integrator; and
short the second terminals of the first and second sampling capacitors together during the sampling phase; and
a second set of switches configured, during an integration phase of the integrator, to connect;
input voltage nodes with the first terminals of the first and second sampling capacitors; and
the first and second input nodes of the amplifier with the second terminals of the first and second sampling capacitors, wherein the first set of switches is open during the integration phase and wherein the second set of switches is open during the sampling phase.
1 Assignment
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Accused Products
Abstract
Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.
21 Citations
31 Claims
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1. A switched-capacitor integrator, comprising:
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an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node; a second integration capacitor coupled between the second output node and the second input node; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured to connect reference voltage nodes with the first terminals of the first and second sampling capacitors during a sampling phase of the integrator; and short the second terminals of the first and second sampling capacitors together during the sampling phase; and a second set of switches configured, during an integration phase of the integrator, to connect; input voltage nodes with the first terminals of the first and second sampling capacitors; and the first and second input nodes of the amplifier with the second terminals of the first and second sampling capacitors, wherein the first set of switches is open during the integration phase and wherein the second set of switches is open during the sampling phase. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A switched-capacitor integrator, comprising:
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an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node; a second integration capacitor coupled between the second output node and the second input node; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured to connect reference voltage nodes with the first terminals of the first and second sampling capacitors during a sampling phase of the integrator; a second set of switches configured, during an integration phase of the integrator, to connect; input voltage nodes with the first terminals of the first and second sampling capacitors; and the first and second input nodes of the amplifier with the second terminals of the first and second sampling capacitors, wherein the first set of switches is open during the integration phase and wherein the second set of switches is open during the sampling phase; and an anti-aliasing filter connected between the input voltage nodes and a portion of the second set of switches, wherein a filter capacitor of the anti-aliasing filter has a substantially larger capacitance than the first sampling capacitor and the second sampling capacitor.
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10. A switched-capacitor integrator, comprising:
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an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node; a second integration capacitor coupled between the second output node and the second input node; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured to connect reference voltage nodes with the first terminals of the first and second sampling capacitors during a sampling phase of the integrator; a second set of switches configured, during an integration phase of the integrator, to connect; input voltage nodes with the first terminals of the first and second sampling capacitors; and the first and second input nodes of the amplifier with the second terminals of the first and second sampling capacitors, wherein the first set of switches is open during the integration phase and wherein the second set of switches is open during the sampling phase; and a third set of switches configured to short at least one of the first or second sampling capacitor between the integration phase and the sampling phase.
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11. A switched-capacitor integrator, comprising:
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an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node; a second integration capacitor coupled between the second output node and the second input node; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured to connect reference voltage nodes with the first terminals of the first and second sampling capacitors during a sampling phase of the integrator; a second set of switches configured, during an integration phase of the integrator, to connect; input voltage nodes with the first terminals of the first and second sampling capacitors; and the first and second input nodes of the amplifier with the second terminals of the first and second sampling capacitors, wherein; the first set of switches is open during the integration phase; the second set of switches is open during the sampling phase; and the first and second sampling capacitors and the second set of switches are part of a digital-to-analog converter (DAC) element having its own control bit; and one or more additional DAC elements replicating the DAC element, each of the additional DAC elements having a control bit.
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12. A switched-capacitor integrator, comprising:
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an amplifier comprising an output node and an input node; an integration capacitor coupled between the output node and the input node of the amplifier; a sampling capacitor having a first terminal and a second terminal; a first set of switches configured to connect a reference voltage node with the first terminal of the sampling capacitor during a sampling phase of the integrator; and a second set of switches configured, during an integration phase of the integrator, to connect; an input voltage node with the first terminal of the sampling capacitor in a first configuration; the input voltage node with the second terminal of the sampling capacitor in a second configuration; the input node of the amplifier with the second terminal of the sampling capacitor in the first configuration; and the input node of the amplifier with the first terminal of the sampling capacitor in the second configuration, wherein the first set of switches is open during the integration phase and wherein the second set of switches is open during the sampling phase. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A switched-capacitor integrator, comprising:
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an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node; a second integration capacitor coupled between the second output node and the second input node; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured to connect reference voltage nodes with the first terminals of the first and second sampling capacitors during reference sampling phases of the integrator; and a second set of switches configured, during integration phases of the integrator, to connect; the second terminals of the first and second sampling capacitors with the first and second input nodes of the amplifier; and the first terminals of the first and second sampling capacitors with outputs of first and second sampling networks, wherein the first set of switches is open during the integration phases, wherein the second set of switches is open during the reference sampling phases, and wherein each of the first and second sampling networks comprises; a first input capacitor having first and second terminals; a second input capacitor having first and second terminals; a third set of switches configured to selectively connect an input node of the sampling network with the first terminal of the first input capacitor; a fourth set of switches configured to connect an output node of the sampling network with the second terminal of the second input capacitor during a first set of the integration phases; a fifth set of switches configured to selectively connect the input node of the sampling network with the first terminal of the second input capacitor; and a sixth set of switches configured to connect the output node of the sampling network with the second terminal of the first input capacitor during a second set of the integration phases. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification