System and method for processing digital data

• US 9,412,145 B2
• Filed: 08/29/2013
• Issued: 08/09/2016
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics Grenoble 2 SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Grenoble 2 SAS (STMicroelectronics NV)
• Inventors: Philippe, Anthony, Cauchy, Xavier, Faugeras, Isabelle, Siron, Didier
• Primary Examiner(s): Cleary, Thomas J
• Application Number:
  US14/013,075
• Publication Number:
  US 20130342763A1
• Time in Patent Office: 1,076 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Claims

1. A system-on-chip (SoC) comprising:

a set of slave processing units comprising programmable slave processing units each configured to execute a programmable video processing function and non-programmable hardware slave processing units each configured to execute a non-programmable pixel processing function;

a data transfer SoC network;

an interconnection module configured to communicate with said data transfer SoC network and to transfer data between said set of slave processing units and said data transfer SoC network; and

a controller configured to control the data transfer.

2. The SoC according to claim 1 wherein the functions comprise video processing functions on a plurality of parallel video input data streams.

3. The SoC according to claim 1 further comprising a shared memory associated with said programmable slave processing units.

4. The SoC according to claim 3 wherein said shared memory comprises a memory internal to said programmable slave processing units.

5. The SoC according to claim 1 wherein said interconnection module is configured to disable slave processing units not in demand.

6. The SoC according to claim 5 wherein said interconnection module is configured to insert into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disable the slave processing unit if there is no active flag in the transmitted signal.

7. The SoC according to claim 1 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer coupled to the groups of slave processing units.

8. The SoC according to claim 7 wherein said interconnection module is configured to insert into a signal transmitted to each slave processing unit a configuration signal of the respective group.

9. The SoC according to claim 1 further comprising at least one other set of slave processing units operating in parallel with said set of slave processing units.

10. A satellite television signal decoder comprising:

a set of slave processing units comprising programmable slave processing units each configured to execute a programmable video processing function and non-programmable hardware slave processing units each configured to execute a non-programmable pixel processing function;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

11. The satellite television signal decoder according to claim 10 wherein the functions comprise video processing functions on a plurality of parallel video input data streams.

12. The satellite television signal decoder according to claim 10 further comprising a shared memory associated with said programmable slave processing units.

13. The satellite television signal decoder according to claim 10 wherein said interconnection module is configured to disable slave processing units not in demand.

14. The satellite television signal decoder according to claim 13 wherein said interconnection module is configured to insert into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disable the slave processing unit if there is no active flag in the transmitted signal.

15. The satellite television signal decoder according to claim 10 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer coupled to the groups of slave processing units.

16. The satellite television signal decoder according to claim 10 further comprising at least one other set of slave processing units operating in parallel with said set of slave processing units.

17. A system-on-chip (SoC) comprising:

a set of slave processing units configured to execute video processing functions on a plurality of parallel video input data streams, and generate a combined video data stream from the plurality of parallel input data streams;

a data transfer SoC network;

an interconnection module configured to communicate with said data transfer SoC network and to transfer data between said set of slave processing units and said data transfer SoC network; and

a controller configured to control the data transfer.

18. The SoC according to claim 17 further comprising a shared memory associated with said set of slave processing units.

19. The SoC according to claim 18 wherein said shared memory comprises a memory internal to said set of slave processing units.

20. The SoC according to claim 17 wherein said interconnection module is configured to disable slave processing units not in demand.

21. The SoC according to claim 20 wherein said interconnection module is configured to insert into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disable the slave processing unit if there is no active flag in the transmitted signal.

22. The SoC according to claim 17 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer coupled to the groups of slave processing units.

23. The SoC according to claim 22 wherein said interconnection module is configured to insert into a signal transmitted to each slave processing unit a configuration signal of the respective group.

24. The SoC according to claim 17 further comprising at least one other set of slave processing units operating in parallel with said set of slave processing units.

25. A satellite television signal decoder comprising:

a set of slave processing units configured to execute video processing functions on a plurality of parallel video input data streams, and generate a combined video data stream from the plurality of parallel input data streams;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

26. The satellite television signal decoder according to claim 25 further comprising a shared memory associated with said set of slave processing units.

27. The satellite television signal decoder according to claim 25 wherein said interconnection module is configured to disable slave processing units not in demand.

28. The satellite television signal decoder according to claim 27 wherein said interconnection module is configured to insert into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disable the slave processing unit if there is no active flag in the transmitted signal.

29. The satellite television signal decoder according to claim 25 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer coupled to the groups of slave processing units.

30. The satellite television signal decoder according to claim 25 further comprising at least one other set of slave processing units operating in parallel with said set of slave processing units.