Writing data to a memory cell

• US 9,412,438 B2
• Filed: 01/24/2014
• Issued: 08/09/2016
• Est. Priority Date: 01/24/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Kai, Hsu, Kuoyuan (Peter), Wang, Bing, Lin, Sung-Chieh
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/163,025
• Publication Number:
  US 20150213880A1
• Time in Patent Office: 928 Days
• Field of Search: 365/154, 365/149
• US Class Current: 1/1
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.

Claims

1. A circuit comprising:

a first transistor having a threshold voltage value, a first terminal, a second terminal, and a third terminal;

a capacitive component having a first capacitive terminal and a second capacitive terminal;

a second transistor having a first terminal, a second terminal, and a third terminal; and

a data line,

wherein

the first terminal of the first transistor is coupled with the first capacitive terminal of the capacitive component and the second terminal of the second transistor;

the second terminal of the first transistor is configured to receive a second-terminal voltage value;

the third terminal of the first transistor is configured to receive a third-terminal voltage value;

the first terminal of the second transistor is coupled with the data line;

the third terminal of the second transistor is configured to receive a second-transistor control signal; and

the first transistor is configured to be on and off to maintain the data line at a data line voltage value.

2. The circuit of claim 1, wherein

the second transistor is configured to be on based on the second-transistor control signal;

the data line is maintained at the data line voltage value based on the threshold voltage value of the first transistor, the second-terminal voltage value of the first transistor, a third terminal voltage value of the first transistor, and a voltage value at the second capacitive terminal.

3. The circuit of claim 1, comprising:

an inverter having an output node,

wherein

the output node of the inverter is coupled with the third terminal of the first transistor; and

the inverter is configured to provide a logical value having a same value as the second-terminal voltage value.

4. The circuit of claim 1, comprising:

a third transistor having a first terminal, a second terminal, and a third terminal; and

a fourth transistor having a first terminal, a second terminal, and a third terminal,

wherein

the first transistor, the second transistor, and the third transistor are each of N-type;

the fourth transistor is of P-type;

the first terminal of the third transistor and the first terminal of the fourth transistor are coupled together and to the third terminal of the first transistor;

the second terminal of the third transistor is coupled with the second terminal of the first transistor; and

the third terminal of the third transistor is coupled with the third terminal of the fourth transistor.

5. The circuit of claim 1, comprising at least one of:

a third transistor having a first terminal, a second terminal, and a third transistor;

or

a fourth transistor having a first terminal, a second terminal, and a third transistor,

wherein

the first terminal of the third transistor is coupled to the data line;

the second terminal of the third transistor is configured to receive a second-terminal voltage value of the third transistor;

the third terminal of the third transistor is configured to receive a third-terminal voltage value of the third transistor;

the first terminal of the fourth transistor is coupled to the first capacitive terminal;

the second terminal of the fourth transistor is configured to receive a second-terminal voltage value of the fourth transistor; and

the third terminal of the fourth transistor is configured to receive a third-terminal voltage value of the fourth transistor.

6. The circuit of claim 1, comprising

a memory cell, wherein the data line carries data to be written to the memory cell.

7. The circuit of claim 1, wherein

the capacitive component is configured to cause a voltage value at the first capacitive terminal to be lower than the second-terminal voltage value of the first transistor.

8. A circuit comprising:

a data line;

a first transistor having a threshold voltage value, a first terminal, a second terminal, and a third terminal; and

a capacitive device having a first capacitive terminal and a second capacitive terminal,

wherein

the first terminal of the first transistor is coupled with the data line and the first capacitive terminal of the capacitive device;

the second terminal of the first transistor is configured to receive a second-terminal voltage value;

the third terminal of the first transistor is configured to receive a third-terminal voltage value, and corresponds to a gate terminal;

the second capacitive terminal of the capacitive device is configured to receive a capacitive voltage value independent of the third-terminal voltage value;

the second-terminal voltage value is independent of the third-terminal voltage value; and

the data line is configured to be clamped at a voltage value based on the threshold voltage value, the second-terminal voltage value, the third-terminal voltage value, and a voltage value at the second capacitive terminal.

9. The circuit of claim 8, comprising

an inverter having an output,

wherein

the output of the inverter is coupled with the third terminal of the first transistor;

and

the inverter is configured to provide a logical value having a same value as the second-terminal voltage value.

10. The circuit of claim 8, comprising:

a second transistor having a first terminal, a second terminal, and a third terminal; and

a third transistor having a first terminal, a second terminal, and a third terminal,

wherein

the first transistor and the second transistor are each of N-type;

the third transistor is of P-type;

the first terminal of the second transistor and the first terminal of the third transistor are coupled together and to the third terminal of the first transistor;

the second terminal of the second transistor is coupled with the second terminal of the first transistor; and

the third terminal of the second transistor is coupled with the third terminal of the third transistor.

11. The circuit of claim 8, wherein

the capacitive device is configured to cause a voltage value at the first capacitive terminal to be lower than the second-terminal voltage value.

12. A method based on a node, comprising:

applying a first logical value to a second terminal of a capacitive component; and

causing the second terminal of the capacitive component to transition from the first logical value to a second logical value different from the first logical value,

wherein

a first terminal of the capacitive component is coupled to the node and a first terminal of a first transistor;

a second terminal of the first transistor receives a second-terminal voltage value;

a third terminal of the first transistor receives a third-terminal voltage value; and

a threshold voltage value of the first transistor, the second-terminal voltage value, and the third-terminal voltage value cause the first transistor to be on and off such that the node is substantially at a node voltage value.

13. The method of claim 12, comprising:

writing to a memory cell based on the node voltage value.

14. The method of claim 12, comprising:

causing the third-terminal voltage value to have the second logical value,

wherein

a voltage value of the second logical value is substantially the same as the second-terminal voltage value.

15. The method of claim 12, comprising:

causing the third terminal of the first transistor to have the third-terminal voltage value by an inverter.

16. The method of claim 15, wherein

the inverter receives a supply voltage value substantially the same as the second-terminal voltage value.

17. The method of claim 12, wherein

the node voltage value is electrically transmitted through a switching device to a data line.

18. The method of claim 17, wherein

the data line is coupled with a first terminal of a second transistor;

a second terminal of the second transistor receives a second-terminal voltage value of the second transistor; and

a third terminal of the second transistor receives a third-terminal voltage value of the second transistor.

19. The method of claim 12, wherein

the node is coupled with a first terminal of a second transistor;

a second terminal of the second transistor receives a second-terminal voltage value of the second transistor; and

a third terminal of the second transistor receives a third-terminal voltage value of the second transistor.

20. The method of claim 12, wherein

the first logical value is a high logical value;

and

the second logical value is a low logical value.