C-element with non-volatile back-up

• US 9,412,448 B2
• Filed: 09/03/2015
• Issued: 08/09/2016
• Est. Priority Date: 09/04/2014
• Status: Active Grant

• Current Assignee: Centre National De La Recherche Scientifique, Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Centre National De La Recherche Scientifique, Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Di Pendina, Grgory, Beigne, Edith, Zianbetov, Eldar
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US14/845,213
• Publication Number:
  US 20160071587A1
• Time in Patent Office: 341 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0072 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node (Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R_min, R_max), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).

Claims

1. A circuit comprising:

a C-element having first and second input nodes and first and second inverters cross-coupled between first and second complementary storage nodes, the second storage node forming an output node of the C-element; and

a non-volatile memory comprising;

a first resistive element having a first terminal coupled to the first storage node;

a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element is coupled to a second terminal of the second resistive element via a write transistor; and

a control block configured, during a backup phase of a data bit stored at the first and second storage nodes to the non-volatile memory, to render conductive the write transistor while different logic levels are applied to the first and second input nodes of the C-element.

2. The circuit of claim 1, wherein the write transistor is adapted to conduct a write current during the backup phase, and wherein the circuit is arranged such that the write current passes through at least one transistor of each of the first and second inverters during the backup phase.

3. The circuit of claim 1, wherein:

the C-element is adapted to receive a first input signal at the first input node and a second input signal at the second input node; and

the first inverter comprises;

first and second transistors having at least one of their control nodes coupled to the first or second storage node;

third and fourth transistors coupled in parallel with each other and coupling the first transistor of the first inverter to a supply voltage rail; and

fifth and sixth transistors coupled in parallel with each other and coupling the second transistor of the first inverter to a ground voltage rail.

4. The circuit of claim 3, wherein the second inverter comprises:

seventh and eighth transistors having at least one of their control nodes coupled to the second or first storage node; and

a ninth transistor coupling a seventh transistor of the second inverter to the supply voltage rail and having its control node coupled to the ground voltage rail.

5. The circuit of claim 4, wherein the fifth and sixth transistors of the first inverter and a eighth transistor of the second inverter are coupled to a common node, the circuit further comprising a tenth transistor coupled between the common node and the ground voltage rail.

6. The circuit of claim 1, further comprising a first read transistor coupled between the first resistive element and a ground voltage rail and a second read transistor coupled between the second resistive element and the ground voltage rail, wherein the control block is further configured to render conductive the first and second read transistors during a restore phase of the data bit stored by the first and second to the storage nodes.

7. The circuit of claim 6, wherein the first read transistor is coupled to the second terminal of the first resistive element, and the second read transistor is coupled to the second terminal of the second resistive element.

8. The circuit of claim 6, wherein the first and second resistive elements each comprise a third terminal, and wherein the first read transistor is coupled to the third terminal of the first resistive element, and the second transistor is coupled to the third terminal of the second resistive element.

9. The circuit of claim 8, wherein said first and second resistive elements are of a spin orbit torque magnetic tunnel junction (SOT-MTJ) type.

10. The circuit of claim 1, wherein at least one of said first and second resistive elements is one of:

a spin transfer torque element with in-plane anisotropy;

a spin transfer torque element with perpendicular-to-plane anisotropy;

a reduction oxide (RedOx) element;

a ferro-electric element; and

a phase change element.

11. An integrated circuit comprising a plurality of asynchronous blocks each comprising the circuit of claim 1.

12. A method of data backup in a circuit comprising:

providing a C-element having first and second input nodes and first and second inverters cross-coupled between first and second complementary storage nodes, the second storage node forming an output node of the C-element;

providing a non-volatile memory comprising;

a first resistive element having a first terminal coupled to the first storage node;

a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element is coupled to a second terminal of the second resistive element via a write transistor; and

rendering conductive the write transistor while different logic levels are applied to the first and second input nodes of the C-element.