Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines

• US 9,412,463 B1
• Filed: 06/02/2015
• Issued: 08/09/2016
• Est. Priority Date: 06/02/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Dong, Yingda
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Tran, Uyen B
• Application Number:
  US14/728,634
• Time in Patent Office: 434 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.

Claims

1. A method, comprising:

while a demarcation voltage is applied to a selected word line among a plurality of word lines, applying a read pass voltage to unselected word lines among the plurality of word lines and applying a respective turn on voltage to a select gate line; and

after the demarcation voltage is applied to the selected word line;

ramping down a voltage of the select gate line from the respective turn on voltage to a respective turn off voltage;

ramping down a voltage of the selected word line at a specified time before the ramping down the voltage of the select gate line if the selected word line is among a predefined subset of the plurality of word lines; and

ramping down the voltage of the selected word line at a time which is after the specified time and no later than a time of the ramping down of the voltage of the select gate line if the selected word line is among a remaining subset of the plurality of word lines.

2. The method of claim 1, wherein:

the predefined subset of the plurality of word lines comprises multiple word lines of the plurality of word lines;

the remaining subset of the plurality of word lines comprises multiple word lines of the plurality of word lines;

each word line of the predefined subset of the plurality of word lines is ramped down with the ramping down of the voltage of the selected word line; and

each word line of the remaining subset of the plurality of word lines is ramped down at the later time.

3. The method of claim 1, wherein:

the selected word line is among the predefined subset of the plurality of word lines.

4. The method of claim 1, wherein:

the selected word line is among the remaining subset of the plurality of word lines.

5. The method of claim 1, wherein:

the predefined subset of the plurality of word lines comprises a set of adjacent word lines which is adjacent to a drain-side of the plurality of word lines.

6. The method of claim 5, wherein:

the set of adjacent word lines comprises no more than 20% of the plurality of word lines.

7. The method of claim 1, wherein:

the predefined subset of the plurality of word lines comprises a first set of adjacent word lines which is adjacent to a drain-side of the plurality of word lines and a second set of adjacent word lines which is adjacent to a source-side of the plurality of word lines, but not word lines which are between the first set of adjacent word lines and the second set of adjacent word lines.

8. The method of claim 7, wherein:

the first set of adjacent word lines comprises no more than 20% of the plurality of word lines; and

the second set of adjacent word lines comprises no more than 20% of the plurality of word lines.

9. The method of claim 1, wherein:

the predefined subset of the plurality of word lines comprises a set of non-adjacent word lines which is adjacent to a drain side of the plurality of word lines.

10. The method of claim 9, wherein:

the set of non-adjacent word lines comprises every other word line in a set of adjacent word lines which is adjacent to the drain side of the plurality of word lines.

11. The method of claim 1, wherein:

the predefined subset of the plurality of word lines comprises a first set of non-adjacent word lines which is adjacent to a drain side of the plurality of word lines and a second set of non-adjacent word lines which is adjacent to a source-side of the plurality of word lines, but not a set of middle word lines which is not adjacent to the drain side of the plurality of word lines or the source-side of the plurality of word lines.

12. The method of claim 1, further comprising:

increasing the voltage of the selected word line from the demarcation voltage to an elevated voltage before the ramping down of the voltage of the selected word line.

13. The method of claim 1, wherein:

the select gate line is at a drain-side of a selected NAND string;

a select gate line is at a source-side of a selected NAND string; and

the voltage of the select gate line at a source-side of the selected NAND string is ramped down from a respective turn on voltage to a respective turn off voltage with the ramping down of the voltage of the select gate line at the drain-side of the selected NAND string.

14. The method of claim 1, wherein the select gate line is at a drain-side of a selected NAND string, the method further comprising, for a drain-side select gate line of an unselected NAND string:

applying a respective turn off voltage while the demarcation voltage is applied to the selected word line;

subsequently applying a respective turn on voltage; and

ramping down a voltage from the respective turn on voltage to a respective turn off voltage with the ramping down of the voltage of the select gate line at the drain-side of the selected NAND string.

15. The method of claim 14, further comprising, for a source-side select gate line of the unselected NAND string:

applying a respective turn off voltage while the demarcation voltage is applied to the selected word line and subsequently applying a respective turn on voltage; and

ramping down a voltage from the respective turn on voltage to the respective turn off voltage with the ramping down of the voltage of the select gate line at the drain-side of the selected NAND string.

16. The method of claim 1, wherein:

the plurality of word lines are connected to memory cells in a selected NAND string;

the selected NAND string comprises a drain-side select gate and a source-side select gate,

the select gate line is connected to the drain-side select gate; and

another select gate line is connected to the source-side select gate.

17. An apparatus, comprising:

means for applying a demarcation voltage to a selected word line among a plurality of word lines;

means for applying a read pass voltage to unselected word lines among the plurality of word lines, a respective turn on voltage to a source-side select gate line at a source-side of the plurality of word lines and a respective turn on voltage to a drain-side select gate line at a drain-side of the plurality of word lines;

means for ramping down voltages of a predefined subset of multiple word lines of the plurality of word lines, before ramping down voltages of a remaining subset of multiple word lines of the plurality of word lines, wherein the selected word line is among the predefined subset of multiple word lines; and

means for ramping down a voltage of the drain-side select gate line from the respective turn on voltage to a respective urn off voltage no sooner than the ramping down of the voltages of the remaining subset of multiple word lines.

18. The apparatus of claim 17, further comprising:

means for ramping down a voltage of the source-side select gate line from the respective turn on voltage to a respective turn off voltage concurrently with the ramping down of the voltage of the drain-side select gate line.

19. An apparatus, comprising:

a plurality of word lines connected to memory cells, wherein the plurality of word lines comprise a selected word line and a plurality of unselected word lines;

a source-side select gate line at a source-side of the plurality of word lines;

a drain-side select gate line at a drain-side of the plurality of word lines; and

a control circuit, the control circuit is configured to;

apply a demarcation voltage to the selected word line;

apply a read pass voltage to the plurality of unselected word lines;

apply a respective turn on voltage to the source-side select gate line and a respective turn on voltage is applied to the drain-side select gate line;

concurrently ramp down the voltage of the selected word line and ramp down a voltage of at least one other word line of the plurality of unselected word lines from the read pass voltage; and

subsequently ramp down voltages of remaining unselected word lines of the plurality of unselected word lines from the read pass voltage and ramp down a voltage of the drain-side select gate line from the respective turn on voltage to a respective turn off voltage.

20. The apparatus of claim 19, wherein:

the plurality of word lines are connected to memory cells in a plurality of NAND strings,

the plurality of NAND strings each comprise a floating body channel; and

the plurality of word lines comprise a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.

21. The apparatus of claim 19, wherein:

the selected word and the at least one other word line are among a set of non-adjacent word lines which is adjacent to a source or drain side of the plurality of word lines; and

the set of non-adjacent word lines comprises no more than 20% of the plurality of word lines.

22. The apparatus of claim 19, wherein:

the selected word and the at least one other word line are among a set of adjacent word lines which is adjacent to a source or drain side of the plurality of word lines; and

the set of adjacent word lines comprises no more than 20% of the plurality of word lines.