Manufacturing method of oxide semiconductor device

• US 9,412,590 B1
• Filed: 08/31/2015
• Issued: 08/09/2016
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chia-Fu, Wu, Chun-Yuan
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/840,055
• Time in Patent Office: 344 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.

Claims

1. A manufacturing method of an oxide semiconductor device, comprising:

forming a barrier layer on a substrate;

performing an annealing process after the step of forming the barrier layer;

performing a first oxygen treatment on the barrier layer after the annealing process

for forming a first oxygen provider layer on the barrier layer, wherein the first oxygen treatment comprises an ozone cleaning treatment; and

forming an oxide semiconductor layer on the first oxygen provider layer.

2. The manufacturing method of claim 1, further comprising:

performing a second oxygen treatment after the step of forming the oxide semiconductor layer, wherein a second oxygen provider layer is formed on the oxide semiconductor layer by the second oxygen treatment.

3. The manufacturing method of claim 2, wherein the second oxygen treatment comprises an oxygen plasma radical treatment or an ozone oxidation treatment.

4. The manufacturing method of claim 1, further comprising:

forming at least one silicon-based field effect transistor on the substrate before the step of forming the barrier layer.

5. The manufacturing method of claim 1, further comprising:

forming a bottom gate electrode on the substrate before the step of forming the barrier layer, wherein a part of the barrier layer is formed on the bottom gate electrode.

6. The manufacturing method of claim 1, further comprising:

forming a top gate electrode above the oxide semiconductor layer.

7. A manufacturing method of an oxide semiconductor device, comprising:

forming a barrier layer on a substrate;

performing an annealing process after the step of forming the barrier layer;

performing a first oxygen treatment on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer;

forming an oxide semiconductor layer on the first oxygen provider layer; and

performing a second oxygen treatment after the step of forming the oxide semiconductor layer, wherein a second oxygen provider layer is formed on the oxide semiconductor layer by the second oxygen treatment.

8. The manufacturing method of claim 7, wherein the first oxygen treatment comprises at least one of an oxygen plasma radical treatment, an ozone oxidation treatment, or an ozone cleaning treatment.

9. The manufacturing method of claim 7, wherein the first oxygen treatment comprises:

forming an auxiliary oxide layer on the barrier layer;

forming the first oxygen provider layer between the auxiliary oxide layer and the barrier layer; and

removing the auxiliary oxide layer after the first oxygen provider layer is formed and before the step of forming the oxide semiconductor layer.

10. The manufacturing method of claim 7, wherein the second oxygen treatment comprises an oxygen plasma radical treatment or an ozone oxidation treatment.

11. The manufacturing method of claim 7, wherein the first oxygen treatment, the step of forming the oxide semiconductor layer, and the second oxygen treatment are in-situ process performed in an identical process chamber.

12. The manufacturing method of claim 7, further comprising:

forming at least one silicon-based field effect transistor on the substrate before the step of forming the barrier layer.