Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

• US 9,412,616 B1
• Filed: 11/16/2015
• Issued: 08/09/2016
• Est. Priority Date: 11/16/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Lim, Kwan-Yong, Sung, Min Gyu, Kim, Ryan Ryoung-Han
• Primary Examiner(s): Menz, Laura
• Application Number:
  US14/942,448
• Time in Patent Office: 267 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Claims

1. A method of forming a double diffusion break (DDB) isolation structure and a single diffusion break (SDB) isolation structure in a semiconductor substrate, comprising:

forming a plurality of sacrificial gate structures above a plurality of fins defined in said semiconductor substrate;

forming a multi-layer patterned masking layer above said substrate, said multi-layer patterned masking layer comprising a first layer of material and a second layer of material positioned above said first layer of material and first and second openings that extend through both of said first and second layers of material, wherein said first opening is positioned above a first area of said substrate between a first and a second of said plurality of sacrificial gate structures where said DDB isolation structure will be formed and said second opening is positioned above a second area of said substrate under a third of said plurality of sacrificial gate structures where said SDB isolation structure will be formed;

performing at least one first process operation through said first opening in both said first and second layers of material to form said DDB break isolation structure in said substrate in said first area;

performing at least one second process operation to remove said second layer of material from above said first layer of material and to expose said first opening formed in said first layer of material; and

performing at least one third process operation through said second opening in said first layer of material to form said SDB isolation structure in said substrate in said second area.

2. The method of claim 1, wherein forming said multi-layer patterned masking layer comprises:

forming said first layer of material above said substrate;

forming said second layer of material on and in contact with said first layer of material;

forming a single patterned etch mask that comprises a photoresist material above said second layer of material, said single patterned etch mask having openings that correspond to both said first and second openings; and

performing at least one etching process through said openings in said single patterned etch mask to define said first and second openings in said first and second material layers.

3. The method of claim 1, wherein performing said at least one first process operation comprises performing at least one first etching process through said first opening in both said first and second layers of material to define a double diffusion break trench in said substrate in an area between said first and second sacrificial gate structures and filling said double diffusion break trench with an insulating material.

4. The method of claim 1, wherein performing said at least one second process operation comprises performing a chemical mechanical polishing process to remove said second layer of material from above an upper surface of said first layer of material and thereafter performing an etching process to remove any material positioned within said second opening in said first layer of material.

5. The method of claim 1, wherein, after forming said multi-layer patterned masking layer, the method further comprises:

performing a conformal deposition process to form a conformal layer of material in said first and second openings, wherein said conformal layer of material substantially fills said second opening; and

performing an isotropic etching process to remove said conformal layer of material from within said first opening while leaving material of said conformal layer of material positioned within said second opening.

6. The method of claim 1, wherein, prior to performing said at least one third process operation, the method comprises performing a trim etching process to increase a lateral width of said second opening in said first layer of material.

7. The method of claim 1, wherein said first opening has a lateral width that is larger than a lateral width of said second opening.

8. The method of claim 1, wherein performing said at least one third process operation comprises:

removing said third sacrificial gate structure so as to define an exposed gate cavity positioned between a sidewall spacer;

performing at least one second etching process through said exposed gate cavity so as to define a single diffusion break trench in said substrate; and

performing at least one process operation through said exposed gate cavity to form said single diffusion break isolation structure in said single diffusion break trench.

9. The method of claim 8, wherein performing said at least one process operation through said exposed gate cavity to form said single diffusion break isolation structure in said single diffusion break trench comprises filling said exposed gate cavity and said single diffusion break isolation trench with an insulation material.

10. The method of claim 9, wherein performing said at least one process operation through said exposed gate cavity to form said single diffusion break isolation structure in said single diffusion break trench further comprises:

performing a recess etching process on said insulating material so as to define a recessed insulating material that has a recessed upper surface positioned within said single diffusion break isolation trench; and

forming an amorphous silicon material within said single diffusion break isolation trench and above said recessed upper surface of said recessed insulating material.

11. The method of claim 8, wherein performing said at least one process operation through said exposed gate cavity to form said single diffusion break isolation structure in said single diffusion break trench comprises:

performing a conformal deposition process to form a layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity; and

forming an amorphous silicon material within said single diffusion break isolation trench on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity.

12. The method of claim 11, further comprising:

performing at least one etching process to remove all remaining sacrificial gate structures and said layer of amorphous silicon material within said single diffusion break isolation trench, wherein said removal of said sacrificial gate structures defines a plurality of replacement gate cavities;

performing a common deposition process to form a layer of high-k insulation material within said replacement gate cavities and on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity; and

performing a common deposition process to form at least one metal layer on said high-k insulation material within said replacement gate cavities and on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity.

13. A method of forming a double diffusion break (DDB) isolation structure and a single diffusion break (SDB) isolation structure in a semiconductor substrate, comprising:

forming a plurality of sacrificial gate structures above a plurality of fins defined in said semiconductor substrate;

forming a multi-layer patterned masking layer above said substrate, said multi-layer patterned masking layer comprising a first layer of material and a second layer of material positioned above said first layer of material and first and second openings that extend through said first and second layers of material, wherein said first opening is positioned above a first area of said substrate between a first and a second of said plurality of sacrificial gate structures where said DDB isolation structure will be formed and said second opening is positioned above a second area of said substrate under a third of said plurality of sacrificial gate structures where said SDB isolation structure will be formed;

performing a conformal deposition process to form a conformal layer of material in said first and second openings, wherein said conformal layer of material substantially fills said second opening;

performing an isotropic etching process to remove said conformal layer of material from within said first opening while leaving material of said conformal layer positioned within said second opening so as to block said second opening;

with said second opening blocked, performing at least one first etching process through said first opening in both said first and second layers of material to define a double diffusion break trench in said substrate;

performing at least one first process operation to form said DDB isolation structure in said double diffusion break trench;

performing at least one second process operation to remove said second layer of material from above an upper surface of said first layer of material and to remove said material of said conformal layer positioned within said second opening in said first layer of material;

performing at least one second etching process through said second opening in said first layer of material to define a single diffusion break trench in said substrate; and

performing at least one third process operation to form said SDB isolation structure in said single diffusion break trench.

14. The method of claim 13, wherein forming said multi-layer patterned masking layer comprises:

forming said first layer of material above said substrate;

forming said second layer of material on and in contact with said first layer of material;

forming a single patterned etch mask that comprises a photoresist material above said second layer of material, said single patterned etch mask having openings that correspond to both said first and second openings; and

performing at least one etching process through said openings in said single patterned etch mask to define said first and second openings in said first and second material layers.

15. The method of claim 13, wherein performing said at least one first process operation to form said DDB isolation structure comprises filling said double diffusion break trench with an insulating material.

16. The method of claim 13, wherein performing said at least one second process operation comprises performing a chemical mechanical polishing process to remove said second layer of material from above said upper surface of said first layer of material and thereafter performing an etching process to remove said material of said conformal layer positioned within said second opening in said first layer of material.

17. The method of claim 13, wherein, prior to performing said at least one second etching process operation, the method comprises performing a trim etching process to increase a lateral width of said second opening in said first layer of material.

18. The method of claim 13, wherein performing said at least one third process operation comprises:

removing said third sacrificial gate structure so as to define an exposed gate cavity positioned between a sidewall spacer;

performing at least one second etching process through said exposed gate cavity so as to define said single diffusion break trench in said substrate; and

performing at least one process operation through said exposed gate cavity to form said single diffusion break isolation structure in said single diffusion break trench.

19. The method of claim 18, wherein performing said at least one process operation through said exposed gate cavity to form said SDB isolation structure in said single diffusion break trench comprises filling said exposed gate cavity and said single diffusion break isolation trench with an insulation material.

20. The method of claim 19, wherein performing said at least one process operation through said exposed gate cavity to form said SDB isolation structure in said single diffusion break trench further comprises:

performing a recess etching process on said insulating material so as to define a recessed insulating material that has a recessed upper surface positioned within said single diffusion break isolation trench; and

forming an amorphous silicon material within said single diffusion break isolation trench and above said recessed upper surface of said recessed insulating material.

21. The method of claim 18, wherein performing said at least one process operation through said exposed gate cavity to form said SDB isolation structure in said single diffusion break trench comprises:

performing a conformal deposition process to form a layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity; and

forming an amorphous silicon material within said single diffusion break isolation trench on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity.

22. The method of claim 21, further comprising:

performing at least one etching process to remove all remaining sacrificial gate structures and said layer of amorphous silicon material within said single diffusion break isolation trench, wherein said removal of said sacrificial gate structures defines a plurality of replacement gate cavities;

performing a common deposition process to form a layer of high-k insulation material within said replacement gate cavities and on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity; and

performing a common deposition process to form at least one metal layer on said high-k insulation material within said replacement gate cavities and on said layer of insulating material that lines said single diffusion break isolation trench and said exposed gate cavity.