Semiconductor device including substrate contact and related method

• US 9,412,640 B2
• Filed: 01/25/2013
• Issued: 08/09/2016
• Est. Priority Date: 01/25/2013
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Nummy, Karen A., Todi, Ravi M.
• Primary Examiner(s): Choi, Calvin
• Application Number:
  US13/749,830
• Publication Number:
  US 20140213053A1
• Time in Patent Office: 1,292 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/945 Trench capacitors

Abstract

A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench;

removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Claims

1. A method of forming a contact on a semiconductor device, the method comprising:

forming a mask on the semiconductor device, the mask exposing at least one contact region including a polysilicon node disposed in a trench of a substrate of the semiconductor device;

performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the polysilicon node within the trench;

removing a set of node films disposed about the polysilicon node and on the sides of the trench, wherein the set of node films include at least two films that extend below the polysilicon node, the polysilicon node being disposed entirely within the substrate and the set of node films; and

forming a contact region within the trench to the substrate and completely covering a top surface of the polysilicon node.

2. The method of claim 1, wherein the contact region includes doped polysilicon.

3. The method of claim 1, wherein the contact region is formed substantially planar relative to the substrate.

4. The method of claim 1, further comprising:

removing the mask following the first substrate contact etch; and

performing a second substrate contact etch on the semiconductor device, the second substrate contact etch recessing the polysilicon node within the semiconductor device.

5. The method of claim 1, wherein the first substrate contact etch forms a top surface on the polysilicon node, the top surface located within the substrate beneath an interface between the substrate and a buried oxide (BOX) region.

6. The method of claim 1, wherein the contact region directly connects to an N+ plate in the semiconductor device.

7. A method of forming a contact on a semiconductor device, the method comprising:

forming a mask on the semiconductor device, the semiconductor device including a set of polysilicon contact nodes and the mask exposing at least one polysilicon contact node disposed within a trench in a substrate of the semiconductor device;

performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the at least one exposed polysilicon contact node within the trench;

removing the mask from the semiconductor device;

performing a second substrate contact etch on the semiconductor device, the second substrate contact etch recessing the set of polysilicon contact nodes within the semiconductor device;

removing a set of node films disposed above the set of polysilicon contact nodes and on the sides of the trench, wherein the set of node films include at least two films that extend below the polysilicon contact node, the polysilicon contact node being disposed entirely within the substrate and the set of node films; and

forming a contact region within the trench above the set of polysilicon contact nodes and completely covering a top surface of the set of polysilicon contact nodes.

8. The method of claim 7, wherein the contact region in the at least one exposed polysilicon contact node connects to the substrate.

9. The method of claim 7, wherein the contact region includes doped polysilicon.

10. The method of claim 7, wherein the contact region is formed substantially planar relative to the substrate.

11. The method of claim 7, wherein the first substrate contact etch forms a top surface on the polysilicon contact node, the top surface located within the substrate beneath an interface between the substrate and a buried oxide (BOX) region.

12. The method of claim 7, wherein the contact region directly connects to an N+ plate in the semiconductor device.

13. A method of forming a contact on a semiconductor device, the method comprising:

masking regions of the semiconductor device other than a set of substrate contacts, the set of substrate contacts including a set of polysilicon contact nodes disposed within a trench in a substrate of the semiconductor device;

etching about the set of substrate contacts on the semiconductor device;

removing a portion of the set of polysilicon contact nodes from the trench; and

removing a set of node films disposed above the set of polysilicon contact nodes and on the sides of the trench following the etching, wherein the set of node films include at least two films that extend below at least one of the set of polysilicon contact nodes, the at least one polysilicon contact node being disposed entirely within the substrate and the set of node films; and

forming a contact region within the trench above the set of contact nodes and completely covering a top surface of the set of polysilicon contact nodes, the contact region substantially connected to the set of contact nodes and the substrate.

14. The method of claim 13, further comprising removing the masked regions of the semiconductor device following the etching.

15. The method of claim 13, wherein the contact region includes doped polysilicon.

16. The method of claim 13, wherein the contact region is formed substantially planar relative to the substrate.

17. The method of claim 13, wherein the etch forms a top surface on the set of polysilicon contact nodes, the top surface located within the substrate beneath an interface between the substrate and a buried oxide (BOX) region.

18. The method of claim 13, wherein the contact region directly connects to an N+ plate in the semiconductor device.