Semiconductor devices and structures

• US 9,412,645 B1
• Filed: 03/07/2014
• Issued: 08/09/2016
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): Le, Don
• Application Number:
  US14/200,061
• Time in Patent Office: 886 Days
• Field of Search: 326 37- 41
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM

Abstract

A method for fabricating semiconductor devices, including: providing a CMOS fabric and metal layers, the metal layers including a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the metal layers providing interconnection for the CMOS fabric, and constructing mask defined connections between the third metal layer and the fourth metal layer, the mask defined connections are substantially similar to antifuse programmed connections of a programmed antifuse programmable device, where the antifuse programmable device is a 3D antifuse programmable device including antifuses and antifuse programming transistors, where the antifuse programming transistors overlay the antifuses, and where the antifuse programming transistors include a monocrystalline channel.

Claims

1. A 3D semiconductor device comprising:

a first layer comprising a first semiconductor layer, said first layer comprising first logic cells;

a first metal layer overlying said first layer;

a second layer comprising a monocrystalline semiconductor layer, said second layer overlying said first metal layer, said second layer comprising second transistors; and

at least one signal between said logic cells,

wherein said signal is buffered by buffer cell, and

wherein said buffer cell comprises at least one of said second transistors.

2. The semiconductor device according to claim 1, further comprising:

power delivery wires to said second transistors,

wherein at least one of said wires is a transistor controlled wire.

3. The semiconductor device according to claim 1, further comprising:

a trench isolation oxide disposed between said second transistors,

wherein said trench isolation oxide has a leakage current between active transistor junctions of less than 1 picoamp per micron at device power supply and 25°

C.

4. The semiconductor device according to claim 1,

wherein said second transistors comprise a high-k gate dielectric.

5. The semiconductor device according to claim 1, further comprising:

a second metal layer disposed between said first metal layer and said second layer,

wherein said first metal layer has a current carrying capacity substantially larger than said second metal layer.

6. The semiconductor device according to claim 1,

wherein at least one contact to said second transistors has lower than 15 ohm/sq contact resistance.

7. A 3D semiconductor device comprising:

a first layer comprising a first semiconductor layer, said first layer comprising first transistors;

a first metal layer overlying said first layer;

a second layer comprising a monocrystalline semiconductor layer, said second layer overlying said first metal layer; and

a second metal layer overlaying said second layer,

wherein said second layer comprises second transistors,

wherein said second transistors comprise a high-k gate dielectric, and

wherein said second layer is less than 2 microns thick.

8. The semiconductor device according to claim 7,

wherein at least one of said second transistors comprises a back-bias structure.

9. The semiconductor device according to claim 7,

wherein said second transistors comprise P type transistors and N type transistors.

10. The semiconductor device according to claim 7,

wherein said first metal layer comprises connections to at least two of said second transistors.

11. The semiconductor device according to claim 7, further comprising:

a third metal layer disposed between said first metal layer and second layer,

wherein said first metal layer has a current carrying capacity substantially larger than said third metal layer.

12. The semiconductor device according to claim 7, further comprising:

power delivery wires,

wherein at least one of said wires comprises a transistor control to control power delivery to at least one of said second transistors.

13. The semiconductor device according to claim 7, further comprising:

a reusable donor wafer.

14. A 3D semiconductor device comprising:

a first layer comprising a first semiconductor layer, said first layer comprising first transistors;

a first metal layer overlying said first layer;

a second layer comprising a monocrystalline semiconductor layer, said second layer overlying said first metal layer;

a second metal layer overlaying said second layer,

wherein said second layer comprises second transistors; and

power delivery wires,

wherein at least one of said wires comprises a transistor control to control power delivery to at least one of said second transistors, and

wherein said second layer is less than 2 microns thick.

15. The semiconductor device according to claim 14,

wherein at least one of said second transistors comprises a back-bias.

16. The semiconductor device according to claim 14,

wherein said second transistors comprise P type transistors and N type transistors.

17. The semiconductor device according to claim 14,

wherein said first metal layer comprises connections to at least two of said second transistors.

18. The semiconductor device according to claim 14, further comprising:

a third metal layer disposed between said first metal layer and second layer,

wherein said first metal layer has a current carrying capacity substantially larger than said third metal layer.

19. The semiconductor device according to claim 14,

wherein said second transistors comprise a high-k gate dielectric.

20. The semiconductor device according to claim 14, further comprising:

a reusable donor wafer.