Via definition scheme

• US 9,412,647 B2
• Filed: 09/11/2013
• Issued: 08/09/2016
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Yen-Cheng, Shih, Chih-Tsung, Yu, Shinn-Sheng, Chen, Jeng-Horng, Yen, Anthony
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US14/024,103
• Publication Number:
  US 20150069622A1
• Time in Patent Office: 1,063 Days
• Field of Search: 257/296, 257/368, 257381-383, 257/586, 257/751, 257/774, 438/700, 438/706, 438/626, 438/638
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.

Claims

1. A method, comprising:

defining a metal pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer;

growing a spacer layer over the metal pattern layer and the first dielectric layer;

forming a metal trench with a metal width in the first dielectric layer; and

forming a via hole with a via width in the second dielectric layer.

2. The method of claim 1, further comprising etching the spacer layer to match the via width.

3. The method of claim 1, wherein the first dielectric layer and the second dielectric layer comprise SiO₂.

4. The method of claim 1, further comprising etching the first dielectric layer to match the via width.

5. The method of claim 4, further comprising removing the spacer layer after etching the first dielectric layer.

6. The method of claim 5, wherein a wet etching process is used to remove the spacer layer.

7. The method of claim 1, further comprising removing the metal pattern layer.

8. The method of claim 1, further comprising filling a metal layer in the metal trench and the via hole.

9. The method of claim 8, further comprising performing a polishing process to remove a portion of the metal layer.

10. The method of claim 1, wherein a dry etching process is used to form the metal trench and the via hole.

11. The method of claim 1, wherein the metal pattern layer comprises photoresist.

12. The method of claim 1, wherein the spacer layer comprises SiN.

13. The method of claim 1, wherein the spacer layer is grown by an atomic layer deposition (ALD) process.

14. An integrated circuit, comprising:

a via having a via width in a first dielectric layer; and

a metal line in a second dielectric layer, the second dielectric layer being disposed over the first dielectric layer,

wherein the metal line has a first width at a first location in a plan view in the second dielectric layer and a second width at a second location in a plan view in the second dielectric layer, the first location not extending directly above the via and the second location extending directly above the via, and the second width being greater than the first width.

15. The integrated circuit of claim 14, wherein the first width is greater than the via width.

16. The integrated circuit of claim 14, further comprising an etch stop layer between the first dielectric layer and the second dielectric layer.

17. The integrated circuit of claim 14, wherein the second width is greater than the first width by 10%-50%.

18. The integrated circuit of claim 14, wherein the metal line has an oval or circular shape directly above the via.

19. A method, comprising:

defining a metal pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer;

growing a spacer layer over the metal pattern layer and the first dielectric layer;

etching the spacer layer to match a pre-determined via width;

etching the first dielectric layer to match the via width;

removing the spacer layer after etching the first dielectric layer;

forming a metal trench with a metal width in the first dielectric layer;

forming a via hole with a via width in the second dielectric layer; and

removing the metal pattern layer.

20. The method of claim 19, further comprising filling metal in the metal trench and the via hole.