Method of manufacturing semiconductor package

• US 9,412,707 B2
• Filed: 05/01/2015
• Issued: 08/09/2016
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hyun-soo, Cho, Tae-je, Ahn, Jung-seok, Lee, In-young
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/702,662
• Publication Number:
  US 20150364432A1
• Time in Patent Office: 466 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Claims

1. A method of manufacturing stacked semiconductor packages, the method comprising:

preparing a wafer substrate comprising a first surface in which an active area is formed and a second surface that is opposite to the first surface;

forming a first through electrode extending by a predetermined length from the second surface toward the first surface;

trimming an edge of the second surface in predetermined intervals and by a predetermined thickness, thereby forming a trimmed wafer substrate surface;

forming a protection layer that covers the second surface and a first portion of the trimmed wafer substrate surface such that a second portion of the trimmed wafer substrate surface is exposed;

forming an adhesive layer on a wafer carrier;

attaching the wafer substrate and the protection layer on the adhesive layer such that the adhesive layer covers an upper surface and a side surface of the protection layer;

exposing an upper portion of the first through electrode by grinding the first surface;

stacking a plurality of semiconductor chips on the first surface, at least one of which is electrically connected to the first through electrode;

forming a molding element to cover the first surface of the wafer substrate and the plurality of semiconductor chips, wherein a diameter of the molding element is greater than a diameter of the wafer substrate and less than respective diameters of the protection layer and the adhesive layer; and

sequentially removing the wafer carrier and the adhesive layer.

2. The method of claim 1, after removing the wafer carrier and the adhesive layer, further comprising performing a singulation process to form individual stacked semiconductor packages by cutting the wafer substrate and the molding element such that each of the stacked semiconductor packages comprises at least one stacked semiconductor chip.

3. The method of claim 1, further comprising after forming the first through electrode, forming a release layer that covers the second surface of the wafer substrate.

4. The method of claim 3, wherein the release layer is formed of polymer.

5. The method of claim 1, further comprising:

forming an access pad on the second surface of the wafer substrate after forming the first through electrode;

forming a passivation layer such that the second surface of the wafer substrate is covered, a side surface of the access pad is surrounded, and an upper surface of the access pad is exposed; and

forming, on the protection layer, an external access terminal, which is electrically connected to the access pad.

6. The method of claim 1, wherein the adhesive layer is formed to cover a side surface of the trimmed edge of the second surface of the wafer substrate, and to cover the second portion of the trimmed wafer substrate surface.

7. The method of claim 1, further comprising cleaning the wafer substrate after trimming the edge of the second surface.

8. The method of claim 1, wherein forming the adhesive layer includes forming the adhesive layer on the wafer carrier by using a spin coating method.

9. The method of claim 1, wherein attaching the wafer substrate and the protection layer on the adhesive layer of the wafer carrier comprises attaching by curing the adhesive layer using a thermal bonding method.

10. The method of claim 1, further comprising after forming the molding element, turning over the wafer substrate and attaching the wafer substrate and the molding element to a dicing tape such that an upper surface of the molding element contacts the dicing tape.

11. A method of manufacturing a semiconductor package, the method comprising:

forming a first semiconductor chip comprising a first surface on which an external access terminal is formed, and a first through electrode that penetrates at least a portion of an area between the first surface and a second surface that is opposite to the first surface;

trimming an edge of the first surface in predetermined intervals and by a predetermined thickness;

forming a first protection layer to cover a side surface of a trimmed edge of the first surface;

forming a second protection layer to cover an exposed upper surface of the trimmed edge of the first surface and an upper surface and a side surface of the first protection layer;

stacking a plurality of second semiconductor chips, at least one of which is connected to the first through electrode, on the second surface;

forming a molding element such that upper surfaces and side surfaces of the plurality of second semiconductor chips are covered and the first and second protection layers are partially exposed;

removing the second protection layer;

trimming an edge of the first protection layer such that an edge of the molding element is partially exposed; and

removing the first protection layer.

12. The method of claim 11, further comprising after removing the first protection layer, performing a singulation process to form an individual semiconductor package by cutting the molding element and the first semiconductor chip such that at least one second semiconductor chip from among the plurality of second semiconductor chips is included in the individual semiconductor package.

13. The method of claim 11, further comprising after forming the external access terminal, forming a release layer on the first surface of the first semiconductor chip and an upper surface of the external access terminal by spin coating an ultraviolet film.

14. The method of claim 11, wherein the first semiconductor chip and the plurality of second semiconductor chips are different types of semiconductor chips.

15. The method of claim 11, wherein the second protection layer is formed as an adhesive layer, and

after forming the second protection layer, the method further comprises attaching the second protection layer to a wafer carrier.

16. A wafer level semiconductor package, comprising:

a circular substrate having a first diameter;

a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter;

a plurality of access terminals arranged on the passivation layer;

a plurality of first access pads each connected to a corresponding one of the access terminals;

a plurality of first through electrodes each electrically connected to a corresponding one of the first access pads, the plurality of first through electrodes extending through the passivation layer and the substrate;

a plurality of second access pads each electrically connected to a corresponding one of the first through electrodes;

a plurality of first semiconductor chips each electrically connected to a corresponding one of the first through electrodes via a corresponding one of the second access pads;

a plurality of second through electrodes each passing through a corresponding one of the plurality of first semiconductor chips;

a plurality of second semiconductor chips each electrically connected to a corresponding one of the second through electrodes; and

a circular molding element covering surfaces of the plurality of first semiconductor chips and the plurality of second semiconductor chips, and covering an active area of the substrate, the circular molding element having a second diameter that is greater than the first diameter.

17. The wafer level semiconductor package of claim 16, further comprising:

a plurality of third through electrodes each passing through a corresponding one of the plurality of second semiconductor chips; and

a plurality of third semiconductor chips each electrically connected to a corresponding one of the third through electrodes.

18. The wafer level semiconductor package of claim 17, wherein the circular molding element covers surfaces of the plurality of third semiconductor chips.

19. The wafer level semiconductor package of claim 16, wherein the molding element includes at least one of an epoxy-based material, a thermosetting material, a thermoplastic material, or a UV processing material.