Wire bond support structure and microelectronic package including wire bonds therefrom

• US 9,412,714 B2
• Filed: 05/30/2014
• Issued: 08/09/2016
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Co, Reynaldo, Zohni, Wael, Saga Cizek, Rizza Lee, Katkar, Rajesh
• Primary Examiner(s): Tsai, H
• Application Number:
  US14/291,874
• Publication Number:
  US 20150348928A1
• Time in Patent Office: 802 Days
• Field of Search: 257/686, 257/723, 257/738, 257/777, 257/784, 257/E23.023
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11318 by dispensing droplets
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

Claims

1. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying a portion of the first surface, thereby defining a first region thereof, wherein a second region of the first surface is defined by another portion of the first surface disposed beyond the at least one microelectronic element;

electrically conductive elements at the first surface of the substrate within the second region;

a support structure having a third surface and a fourth surface remote from the third surface, the support structure overlying the second region of the first surface and not overlying the first region of the first surface, wherein the third surface faces the first surface, the support structure having second and third electrically conductive elements exposed respectively at the third and fourth surfaces, the second electrically conductive elements being electrically connected to the conductive elements at the first surface of the substrate in the first region; and

wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases,

an integral continuous encapsulation region contacting the support structure, the substrate and at least edge surfaces of the wire bonds.

2. The microelectronic package of claim 1

wherein the encapsulation region extends from the first surface and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation region, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.

3. The microelectronic package of claim 1 further comprising:

a redistribution layer extending along at least a portion of at least one of the third surface or the fourth surface,

wherein the redistribution layer includes a redistribution substrate having a fifth surface adjacent the least one of the third surface or the fourth surface and a sixth surface remote from the fifth surface, first electrically conductive pads at the fifth surface of the redistribution substrate aligned with and contacting respective ones of the second or third electrically conductive elements at the third or fourth surfaces, and second electrically conductive pads at the sixth surface of the redistribution substrate electrically connected to the first conductive pads.

4. The microelectronic package of claim 1, wherein the second conductive elements are bonded to respective ones of the conductive elements at the first surface of the substrate by a conductive bonding material.

5. The microelectronic package of claim 1, wherein conductive vias of the support structure electrically connect ones of the bases of the wire bonds with respective ones of the second conductive elements at the third surface of the support structure.

6. The microelectronic package of claim 1, wherein the encapsulation region encapsulates the at least one microelectronic element.

7. The microelectronic package of claim 1, wherein the encapsulation region has a major surface remote from the first surface of the substrate, and ends of the wire bonds project above the major surface of the encapsulation region.

8. The microelectronic package of claim 1, wherein the support structure is in form of a frame surrounding an open, interior region having dimensions sufficient to receive the at least one microelectronic element therein.

9. The microelectronic package of claim 8, wherein the support structure surrounds the at least one microelectronic element.

10. The microelectronic package of claim 9, wherein the encapsulation region entirely covers the fourth surface of the support structure and the wire bonds extend through the encapsulation region.