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Post-CMOS processing and 3D integration based on dry-film lithography

  • US 9,412,728 B2
  • Filed: 07/19/2013
  • Issued: 08/09/2016
  • Est. Priority Date: 08/03/2012
  • Status: Expired due to Fees
First Claim
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1. A method for performing a post processing pattern on a diced chip having a footprint, comprising the steps of:

  • providing a support wafer;

    applying a first dry film photoresist to the support wafer;

    positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist;

    expose the mask and the first dry film photoresist to UV radiation;

    remove the mask;

    photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip;

    positioning the diced chip inside the cavity;

    applying a second dry film photoresist to the first film photoresist and the diced chip; and

    expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.

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