MOSFET with integrated schottky diode

• US 9,412,733 B2
• Filed: 06/25/2013
• Issued: 08/09/2016
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Calafut, Daniel, Lee, Yeeheng
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): SKYLES, TIFNEY L
• Application Number:
  US13/926,880
• Publication Number:
  US 20140374824A1
• Time in Patent Office: 1,141 Days
• Field of Search: 257/334
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66257 Schottky transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 : the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A Schottky structure comprising:

two trenches formed into a semiconductor material and spaced apart from each other by a mesa, wherein each trench is lined with a dielectric material, and wherein a first portion of conductive material is disposed along a first sidewall of each trench and a second portion of conductive material is disposed along a second sidewall of each trench, and wherein the first and second portions of conductive material are electrically isolated from each other, wherein the first portion of conductive material in the first trench is maintained at a gate potential; and

one or more Schottky contacts formed between the outermost walls of the two trenches, wherein the one or more Schottky contacts extend in a direction parallel to the two trenches.

2. The Schottky structure of claim 1, wherein the two trenches are formed in an active region of a MOSFET device.

3. The Schottky structure of claim 2, wherein the first portion of conductive material in the first trench is maintained at a gate potential, the second portion of conductive material in the first trench is maintained at a source potential, the first portion of conductive material in the second trench is maintained at the source potential, and the second portion of conductive material in the second trench is maintained at the gate potential.

4. The Schottky structure of claim 1, wherein the two trenches are formed in a termination region of a MOSFET device.

5. The Schottky structure of claim 4, wherein the first portion of conductive material in the first trench is maintained at a gate potential, the second portion of conductive material in the first trench is maintained at a source potential, the first portion of conductive material in the second trench is maintained at the source potential, and the second portion of conductive material in the second trench is maintained at drain potential.

6. The Schottky structure of claim 1, wherein a width of the mesa between the two trenches is equal to a width of a mesa between device trenches formed in the semiconductor material.

7. The Schottky structure of claim 1, wherein a width of the mesa between the two trenches is smaller than a device mesa separating device trenches.

8. The Schottky structure of claim 7, wherein the width of the mesa between the two trenches is between one fourth and three fourths of the width of the device mesa.

9. The Schottky structure of claim 1, wherein the Schottky contact is formed in the mesa between the two trenches.

10. The Schottky structure of claim 9, wherein the Schottky contact further contacts the conductive portions in each trench proximate to the mesa.

11. The Schottky structure of claim 1, wherein one of the one or more Schottky contacts is formed in one of the trenches between the first conductive portion and the second conductive portion.

13. The Schottky structure of claim 1, wherein a first Schottky contact is formed in the mesa between the two trenches and a second Schottky contact is formed in at least one of the trenches between the first conductive portion and the second conductive portion.

14. The Schottky structure of claim 13, wherein the second Schottky contact is configured as a closed cell structure.

15. The Schottky structure of claim 1, wherein the Schottky structure is integrated into a bipolar transistor, insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET), a diode, a resistor or a capacitor.

12. A Schottky structure comprising:

two trenches formed into a semiconductor material and spaced apart from each other by a mesa, wherein each trench is lined with a dielectric material, and wherein a first portion of conductive material is disposed along a first sidewall of each trench and a second portion of conductive material is disposed along a second sidewall of each trench, and wherein the first and second portions of conductive material are electrically isolated from each other; and

two or more Schottky contacts formed between the outermost walls of the two trenches, wherein the two or more Schottky contacts extend in a direction parallel to the two trenches, wherein two of the two or more Schottky contacts are formed in the two trenches respectively between the first conductive portions and the second conductive portions, wherein at least one of the two or more Schottky contacts is deactivated by selectively doping the semiconductor material with dopants configured to prevent a Schottky diode from forming.