DC-DC converter and semiconductor device

• US 9,412,762 B2
• Filed: 07/29/2014
• Issued: 08/09/2016
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Takahashi, Kei
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Sabur, Alia
• Application Number:
  US14/445,370
• Publication Number:
  US 20150035514A1
• Time in Patent Office: 742 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H02M 3/33553 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

Claims

1. A semiconductor device comprising:

a control circuit comprising;

a holding circuit comprising a first transistor; and

an operational amplifier;

a second transistor; and

a first output terminal,

wherein a first terminal of the first transistor is electrically connected to the operational amplifier,

wherein an output terminal of the operational amplifier is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to the first output terminal,

wherein the first transistor comprises a first oxide semiconductor film comprising a channel formation region,

wherein the second transistor comprises a second oxide semiconductor film comprising a channel formation region,

wherein each of the first oxide semiconductor film and the second oxide semiconductor film comprises In, M, and Zn,

wherein an atomic ratio of In to M in the second oxide semiconductor film is higher than an atomic ratio of In to M in the first oxide semiconductor film, and

wherein M is at least one of Ga, Y, Zr, La, Ce, and Nd.

2. The semiconductor device according to claim 1,

wherein the holding circuit is configured to hold a bias potential supplied to the operational amplifier,

wherein the operational amplifier is configured to generate a control signal supplied to the gate of the second transistor, and

wherein the second transistor is configured to supply a voltage from the first output terminal.

3. The semiconductor device according to claim 2,

wherein the holding circuit comprises a capacitor, and

wherein the capacitor is configured to hold a charge corresponding to the bias potential.

4. The semiconductor device according to claim 1, further comprising a coil,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil, and

wherein a second terminal of the coil is electrically connected to the first output terminal.

5. The semiconductor device according to claim 1, further comprising a coil, a diode, and a second output terminal,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil and a first terminal of the diode,

wherein a second terminal of the second transistor is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first output terminal, and

wherein a second terminal of the diode is electrically connected to the second output terminal.

6. The semiconductor device according to claim 1, further comprising a coil and a second output terminal,

wherein a first terminal of the coil is electrically connected to the first terminal of the second transistor, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.

7. The semiconductor device according to claim 1, further comprising a coil, a diode, and a second output terminal,

wherein a first terminal of the coil is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first terminal of the second transistor and a first terminal of the diode,

wherein a second terminal of the diode is electrically connected to the first output terminal, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.

8. A semiconductor device comprising:

a control circuit comprising;

a holding circuit comprising a first transistor; and

an operational amplifier;

a second transistor; and

a first output terminal,

wherein a first terminal of the first transistor is electrically connected to the operational amplifier,

wherein an output terminal of the operational amplifier is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to the first output terminal,

wherein the first transistor comprises a first oxide semiconductor film comprising a channel formation region and a pair of first gate electrodes between which the first oxide semiconductor film is provided,

wherein the second transistor comprises a second oxide semiconductor film comprising a channel formation region and a pair of second gate electrodes between which the second oxide semiconductor film is provided,

wherein a potential of one of the pair of first gate electrodes is lower than a potential of the other of the pair of first gate electrodes,

wherein the pair of second gate electrodes is electrically connected to each other,

wherein the first oxide semiconductor film and the second oxide semiconductor film each contain In, M, and Zn, and

wherein M is at least one of Ga, Y, Zr, La, Ce, and Nd.

9. The semiconductor device according to claim 8,

wherein the holding circuit is configured to hold a bias potential supplied to the operational amplifier,

wherein the operational amplifier is configured to generate a control signal supplied to the gate of the second transistor, and

wherein the second transistor is configured to supply a voltage from the first output terminal.

10. The semiconductor device according to claim 9,

wherein the holding circuit comprises a capacitor, and

wherein the capacitor is configured to hold a charge corresponding to the bias potential.

11. The semiconductor device according to claim 8, further comprising a coil,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil, and

wherein a second terminal of the coil is electrically connected to the first output terminal.

12. The semiconductor device according to claim 8, further comprising a coil, a diode, and a second output terminal,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil and a first terminal of the diode,

wherein a second terminal of the second transistor is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first output terminal, and

wherein a second terminal of the diode is electrically connected to the second output terminal.

13. The semiconductor device according to claim 8, further comprising a coil and a second output terminal,

wherein a first terminal of the coil is electrically connected to the first terminal of the second transistor, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.

14. The semiconductor device according to claim 8, further comprising a coil, a diode, and a second output terminal,

wherein a first terminal of the coil is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first terminal of the second transistor and a first terminal of the diode,

wherein a second terminal of the diode is electrically connected to the first output terminal, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.

15. A semiconductor device comprising:

a control circuit comprising;

a holding circuit comprising a first transistor; and

an operational amplifier;

a second transistor; and

a first output terminal,

wherein a first terminal of the first transistor is electrically connected to the operational amplifier,

wherein an output terminal of the operational amplifier is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to the first output terminal,

wherein the first transistor comprises a first oxide semiconductor film comprising a channel formation region,

wherein the second transistor comprises a second oxide semiconductor film comprising a channel formation region,

wherein the first oxide semiconductor film comprises In, M, and Zn,

wherein M is at least one of Ga, Y, Zr, La, Ce, and Nd, and

wherein the second oxide semiconductor film comprises at least one of In and Zn.

16. The semiconductor device according to claim 15,

wherein the holding circuit is configured to hold a bias potential supplied to the operational amplifier,

wherein the operational amplifier is configured to generate a control signal supplied to the gate of the second transistor, and

wherein the second transistor is configured to supply a voltage from the first output terminal.

17. The semiconductor device according to claim 16,

wherein the holding circuit comprises a capacitor, and

wherein the capacitor is configured to hold a charge corresponding to the bias potential.

18. The semiconductor device according to claim 15, further comprising a coil,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil, and

wherein a second terminal of the coil is electrically connected to the first output terminal.

19. The semiconductor device according to claim 15, further comprising a coil, a diode, and a second output terminal,

wherein the first terminal of the second transistor is electrically connected to a first terminal of the coil and a first terminal of the diode,

wherein a second terminal of the second transistor is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first output terminal, and

wherein a second terminal of the diode is electrically connected to the second output terminal.

20. The semiconductor device according to claim 15, further comprising a coil and a second output terminal,

wherein a first terminal of the coil is electrically connected to the first terminal of the second transistor, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.

21. The semiconductor device according to claim 15, further comprising a coil, a diode, and a second output terminal,

wherein a first terminal of the coil is electrically connected to a power source,

wherein a second terminal of the coil is electrically connected to the first terminal of the second transistor and a first terminal of the diode,

wherein a second terminal of the diode is electrically connected to the first output terminal, and

wherein a second terminal of the second transistor is electrically connected to the second output terminal.