Semiconductor device and manufacturing method of the same

• US 9,412,766 B2
• Filed: 05/20/2014
• Issued: 08/09/2016
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakakura, Masayuki, Yamazaki, Shunpei
• Primary Examiner(s): Kim, Su C
• Application Number:
  US14/282,039
• Publication Number:
  US 20140252360A1
• Time in Patent Office: 812 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 2924/13069 : Thin film transistor [TFT]
• CPC Class Codes: H10K 59/1201 : Manufacture or treatment
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/88 : Dummy elements, i.e. elements having non-functional features

Abstract

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Claims

1. A semiconductor device comprising:

a substrate;

a first transistor over the substrate;

a second transistor over the substrate and electrically connected to the first transistor;

a first wiring;

a second wiring overlaps the first wiring;

an insulating film over the second wiring; and

a light-emitting element,

wherein one of a source and a drain of the second transistor is electrically connected to the light-emitting element,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein the first wiring comprises a first region and a second region,

wherein the first region extends in first direction, and the second region projects to second direction from the first region,

wherein the second wiring comprises a third region which extends in the second direction,

wherein portion of the second region functions as a gate of the first transistor,

wherein the third region entirely overlaps the second region, and

wherein a length of the third region in the first direction is larger than a length of the second region in the first direction.

2. The semiconductor device according to claim 1,

wherein the first transistor comprises a semiconductor layer,

wherein the semiconductor layer comprises a fourth region, and

wherein the second region overlaps the fourth region.

3. The semiconductor device according to claim 2,

wherein the semiconductor layer further comprises a fifth region, and

wherein the first region overlaps the fifth region.

4. The semiconductor device according to claim 3,

wherein the fourth region extends in the first direction, and

wherein the fifth region extends in the second direction.

5. The semiconductor device according to claim 1,

wherein the second wiring further comprises a sixth region, and

wherein the fifth region projects to the first direction.

6. The semiconductor device according to claim 1, wherein the substrate is a plastic substrate.

7. The semiconductor device according to claim 1, wherein the second wiring comprises a multi-layered film.

8. A display module comprising the semiconductor device according to claim 1 and a FPC.

9. An electronic device comprising the display module according to claim 8 and an operation switch.

10. A semiconductor device comprising:

a substrate;

a first transistor over the substrate;

a second transistor over the substrate and electrically connected to the first transistor;

a first wiring;

a second wiring overlaps the first wiring;

an insulating film over the second wiring; and

a light-emitting element,

wherein one of a source and a drain of the second transistor is electrically connected to the light-emitting element,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein the first wiring comprises a first region and a second region,

wherein the second wiring comprises a third region,

wherein a long side direction of the first region is parallel to a first direction,

wherein a long side direction of the second region is parallel to a second direction,

wherein a long side direction of the third region is parallel to the second direction,

wherein portion of the second region functions as a gate of the first transistor,

wherein the third region entirely overlaps the second region, and

wherein a length of the third region in the first direction is larger than a length of the second region in the first direction.

11. The semiconductor device according to claim 10,

wherein the first transistor comprises a semiconductor layer,

wherein the semiconductor layer comprises a fourth region, and

wherein the second region overlaps the fourth region.

12. The semiconductor device according to claim 11,

wherein the semiconductor layer further comprises a fifth region, and

wherein the first region overlaps the fifth region.

13. The semiconductor device according to claim 12,

wherein the fourth region extends in the first direction, and

wherein the fifth region extends in the second direction.

14. The semiconductor device according to claim 10,

wherein the second wiring further comprises a sixth region, and

wherein the fifth region projects to the first direction.

15. The semiconductor device according to claim 10, wherein the substrate is a plastic substrate.

16. The semiconductor device according to claim 10, wherein the second wiring comprises a multi-layered film.

17. A display module comprising the semiconductor device according to claim 10 and a FPC.

18. An electronic device comprising the display module according to claim 17 and an operation switch.