Making multilayer 3D capacitors using arrays of upstanding rods or ridges

• US 9,412,806 B2
• Filed: 06/13/2014
• Issued: 08/09/2016
• Est. Priority Date: 06/13/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Wang, Liang, Katkar, Rajesh, Shen, Hong, Uzoh, Cyprian Emeka
• Primary Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US14/304,535
• Publication Number:
  US 20150364538A1
• Time in Patent Office: 788 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15184 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16151 Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16251 Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate

Abstract

In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Claims

1. A method for making a capacitor, the method comprising:

providing a substrate having a surface;

depositing a first electroconductive layer on the surface;

bonding an end of at least one upstanding wire to the first electroconductive layer by a first bond comprising at least one of a molten ball bond and an ultrasonic bond;

coating the first electroconductive layer and the at least one wire with a dielectric layer, which comprises at least part of capacitor dielectric for the capacitor; and

depositing a second electroconductive layer on the dielectric layer, the second electroconductive layer comprising at least part of a first capacitor electrode for the capacitor.

2. The method of claim 1, wherein the bonding comprises bonding respective ends of an array of upstanding wires to the first electroconductive layer.

3. The method of claim 1, wherein the at least one wire comprises gold (Au), copper (Cu) or aluminum (Al).

4. The method of claim 1, wherein the first bond comprises a stitch bond.

5. The method of claim 1, wherein the first bond comprises a molten ball bond.

6. The method of claim 1 wherein the at least one wire comprises at least part of a second capacitor electrode for the capacitor.

7. The method of claim 1 wherein said bonding comprises, for the at least one wire:

providing a supply of wire in a bonding tool, the supply of wire comprising the at least one wire exposed at an opening of a capillary of the bonding tool;

bonding the at least one wire to the first electroconductive layer; and

severing the at least one wire from the supply of wire.

8. A method for making a capacitor, the method comprising:

providing a substrate having a surface;

depositing a first electroconductive layer on the surface;

bonding an end of at least one upstanding wire to the first electroconductive layer;

coating the first electroconductive layer and the at least one wire with a dielectric layer; and

depositing a second electroconductive layer on the dielectric layer;

wherein the at least one wire comprises gold (Au), copper (Cu) or aluminum (Al); and

wherein the at least one wire is plated with palladium (Pd).

9. A structure comprising:

a surface;

one or more first structures located on the surface, each first structure extending away from the surface, each first structure comprising;

a wire bonded to the surface by a first bond comprising at least one of a molten ball bond and a stitch bond;

one or more dielectric features covering the wire, each dielectric feature comprising at least part of a capacitor dielectric for a capacitor; and

one or more electroconductive layers each of which overlies at least one said dielectric layer and comprises at least part of a first capacitor electrode for the capacitor.

10. The structure of claim 9, wherein in at least one said first structure, the wire is bonded to the surface by the respective first bond comprising the stitch bond.

11. The structure of claim 9, wherein in at least one said first structure, the wire is bonded to the surface by the respective first bond comprising the molten ball bond.

12. The structure of claim 9 wherein in at least one said first structure, the wire comprises at least part of a second capacitor electrode for the capacitor.

13. The structure of claim 9 wherein the one or more first structures are a plurality of first structures.

14. A method for making a capacitor, the method comprising:

providing a first electroconductive layer;

providing a supply of wire comprising a portion exposed at an opening of a capillary of a bonding tool;

bonding the portion of the supply of wire to the first electroconductive layer to form a bond between the supply of wire and the first electroconductive layer;

severing a length of wire from the supply of wire, the length of wire being a wire bonded to the first electroconductive layer by the bond and comprising a longitudinal segment extending away from the bond and away from the first electroconductive layer;

coating the longitudinal segment with a dielectric which comprises at least part of a capacitor dielectric for the capacitor; and

coating the dielectric with a second electroconductive layer, the second electroconductive layer comprising at least part of a first capacitor electrode for the capacitor.

15. The method of claim 14 wherein the wire comprises at least part of a second capacitor electrode for the capacitor.