Structure and formation method of FinFET device

• US 9,412,814 B2
• Filed: 12/24/2014
• Issued: 08/09/2016
• Est. Priority Date: 12/24/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tung-Ying, Huang, Yu-Lien
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/582,975
• Publication Number:
  US 20160190243A1
• Time in Patent Office: 594 Days
• Field of Search: 257/295, 257/288
• US Class Current: 1/1
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure and a source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device structure further includes an isolation layer between the source/drain structure and the semiconductor substrate.

Claims

1. A semiconductor device structure, comprising:

a semiconductor substrate;

a fin structure over the semiconductor substrate;

a gate stack covering a portion of the fin structure;

a source/drain structure over the fin structure and adjacent to the gate stack; and

an isolation layer between the source/drain structure and the semiconductor substrate, wherein the isolation layer is directly under the source/drain structure.

2. The semiconductor device structure as claimed in claim 1, wherein the isolation layer is between the source/drain structure and the fin structure.

3. The semiconductor device structure as claimed in claim 1, wherein the isolation layer is in direct contact with the source/drain structure.

4. The semiconductor device structure as claimed in claim 1, wherein the isolation layer is in direct contact with the fin structure.

5. The semiconductor device structure as claimed in claim 1, wherein the isolation layer is made of silicon germanium oxide.

6. The semiconductor device structure as claimed in claim 1, further comprising a semiconductor material layer between the isolation layer and the source/drain structure.

7. The semiconductor device structure as claimed in claim 6, wherein the source/drain structure has an atomic concentration of germanium greater than that of the semiconductor material layer.

8. The semiconductor device structure as claimed in claim 1, wherein the isolation layer has a bottom surface curved towards the source/drain structure.

9. The semiconductor device structure as claimed in claim 1, further comprising a second fin structure between the fin structure and the semiconductor substrate, wherein materials of the fin structure and the second fin structure are different from each other.

10. The semiconductor device structure as claimed in claim 9, further comprising a second isolation layer between the fin structure and the second fin structure, wherein the second isolation layer is in direct contact with the second fin structure and the first fin structure.

11. The semiconductor device structure as claimed in claim 1, wherein the isolation layer has a V-shaped profile.

12. The semiconductor device structure as claimed in claim 1, wherein the isolation layer has a top surface curved towards the fin structure under the isolation layer.

13. The semiconductor device structure as claimed in claim 1, further comprising a recess formed above the fin structure, wherein a portion of the isolation layer is disposed on a sidewall of the recess.

14. A semiconductor device structure, comprising:

a semiconductor substrate;

a fin structure over the semiconductor substrate;

a germanium-containing fin structure over the fin structure;

a gate stack covering a portion of the germanium-containing fin structure;

a source/drain structure over the germanium-containing fin structure and adjacent to the gate stack; and

an isolation layer between the source/drain structure and the semiconductor substrate, wherein the isolation layer is directly under the source/drain structure.

15. The semiconductor device structure as claimed in claim 14, wherein the isolation layer is between the source/drain structure and the germanium-containing fin structure.

16. The semiconductor device structure as claimed in claim 15, further comprising a second isolation layer between the fin structure and the germanium-containing fin structure.

17. The semiconductor device structure as claimed in claim 14, wherein the isolation layer is between the fin structure and the germanium-containing fin structure.

18. The semiconductor device structure as claimed in claim 14, wherein a portion of the source/drain structure extends into the fin structure.

19. The semiconductor device structure as claimed in claim 14, further comprising a semiconductor material layer between the isolation layer and the source/drain structure.

20. The semiconductor device structure as claimed in claim 19, wherein the source/drain structure has an atomic concentration of germanium greater than that of the semiconductor material layer.