Trench power MOSFET

• US 9,412,844 B2
• Filed: 10/08/2015
• Issued: 08/09/2016
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Liu, Ruey-Hsin, Su, Po-Chih
• Primary Examiner(s): Parker, Allen
• Assistant Examiner(s): BRADLEY, STEPHEN M
• Application Number:
  US14/878,284
• Publication Number:
  US 20160027900A1
• Time in Patent Office: 306 Days
• Field of Search: 257330-335, 438/259
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Claims

1. A method comprising:

forming a trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;

forming a conductive layer extending into the trench and on an edge of the trench;

etching the semiconductor region to extend the trench deeper into the semiconductor region, with the conductive layer acting as an etching mask;

performing a tilt implantation using the conductive layer as a part of an implantation mask to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type;

forming a first dielectric layer on a bottom and sidewalls of the trench;

forming a field plate in the trench and over a bottom portion of the first dielectric layer;

forming a second dielectric layer over the field plate; and

forming a main gate in the trench and over the second dielectric layer.

2. The method of claim 1, wherein the forming the conductive layer comprises:

depositing a blanket conductive layer comprising horizontal portions and vertical portions, wherein the trench has a remaining portion unfilled by the blanket conductive layer; and

etching the blanket conductive layer to remove the horizontal portions, wherein parts of the vertical portions in the trench remain as the conductive layer.

3. The method of claim 2, wherein a top end of the conductive layer is lower than a top surface of the semiconductor region.

4. The method of claim 1, wherein the DD region is overlapped by the conductive layer.

5. The method of claim 1, wherein the main gate is joined to the conductive layer to form a continuous conductive region.

6. The method of claim 1 further comprising forming a mask layer at the bottom of the trench, wherein a topmost end of the mask layer is lower than a top of the trench, with the tilt implantation performed using the mask layer as an additional implantation mask, and the DD region has a bottom surface higher than the bottom of the trench.

7. The method of claim 1 further comprising:

depositing an inter-layer dielectric over the main gate; and

forming a source region and a drain region on opposite sides of the semiconductor region.

8. The method of claim 1 further comprising forming a body region of a second conductivity type opposite to the first conductivity type, wherein the body region contacts a sidewall of the DD region.

9. A method comprising:

etching a semiconductor region to form a trench;

forming a mask layer at a bottom of the trench;

performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the mask layer as an additional implantation mask, wherein a topmost surface of the mask layer defines a bottom surface of the DD region, wherein the DD region has portions on opposite sides of the trench, and a bottom surface of the DD region is higher than a bottom of the trench;

forming a first dielectric layer lining the bottom and sidewalls of the trench, with the first dielectric layer having an edge contacting an edge of the DD region;

forming a field plate in the trench and over a bottom portion of the first dielectric layer;

forming a second dielectric layer over the field plate; and

forming a main gate in the trench and over the second dielectric layer.

10. The method of claim 9, wherein the trench comprises a portion that is overlapped by the DD region.

11. The method of claim 9, wherein the tilt implantation is performed with a conductive layer in the trench as an implantation mask.

12. The method of claim 11 further comprising:

depositing a blanket conductive layer comprising horizontal portions and vertical portions; and

etching the blanket conductive layer to remove the horizontal portions, wherein parts of the vertical portions in the trench remain as the conductive layer.

13. The method of claim 9, wherein a bottom surface of the first dielectric layer is in physical contact with a top surface of the semiconductor region.

14. The method of claim 9 further comprising removing the mask layer after the tilt implantation.

15. The method of claim 9, wherein the top surface of the mask layer is between a top of the trench and the bottom of the trench.

16. A method comprising:

etching a semiconductor region to form a trench;

oxidizing a surface layer of the semiconductor region to form an oxide layer, wherein the surface layer is exposed to the trench;

forming a conductive layer in the trench and on sidewalls of the trench, wherein the conductive layer has a bottom contacting a top surface of the oxide layer;

etching the oxide layer and the semiconductor region to extend the trench deeper into the semiconductor region, with the conductive layer acting as an etching mask;

forming a mask layer extending to a bottom of the trench, wherein the mask layer has a topmost surface at an intermediate level between a top surface of the semiconductor region and the bottom of the trench;

performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the mask layer as an implantation mask, wherein the topmost surface defines a position of a bottom surface of the DD region, wherein the DD region is overlapped by the conductive layer;

implanting the semiconductor region to form a body region, with the body region and the DD region having opposite conductivity types, wherein the body region has a bottom end at an intermediate level between a top surface and a bottom surface of the DD region, and the body region contacts a sidewall of the DD region; and

forming a drain region overlapped by the DD region, wherein the drain region is electrically connected to the DD region.

17. The method of claim 16, wherein when the tilt implantation is performed, the conductive layer has a top surface lower than a top surface of the semiconductor region.

18. The method of claim 16, wherein when the tilt implantation is performed, a bottom surface of the conductive layer is higher than a bottom of the trench.

19. The method of claim 16 further comprising:

forming a first dielectric layer on a bottom and sidewalls of the trench, with the first dielectric layer having an edge contacting an edge of the DD region;

forming a field plate in the trench and over a bottom portion of the first dielectric layer;

forming a second dielectric layer over the field plate; and

forming a main gate in the trench and over the second dielectric layer.

20. The method of claim 16, wherein the bottom surface of the DD region is substantially coplanar with the topmost surface of the mask layer.