Semiconductor structure with stress-reducing buffer structure

• US 9,412,902 B2
• Filed: 02/22/2015
• Issued: 08/09/2016
• Est. Priority Date: 02/22/2014
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Dobrinsky, Alexander, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Ghyka, Alexander
• Application Number:
  US14/628,281
• Publication Number:
  US 20150243841A1
• Time in Patent Office: 534 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

Claims

1. A method of fabricating a semiconductor structure, the method including:

selecting a set of growth parameters for growing a buffer structure, wherein the set of growth parameters are configured to achieve a target effective lattice constant a for the buffer structure;

growing the buffer structure using the selected set of growth parameters, wherein the growing the buffer structure includes;

growing a buffer layer; and

growing an intermediate layer directly on the buffer layer, wherein the intermediate layer includes a plurality of sub-layers having alternating tensile and compressive stresses, wherein the stresses are adjusted by varying a V/III ratio used during the growth of the plurality of sub-layers; and

growing a set of semiconductor layers on the buffer structure, wherein the target effective lattice constant a causes an overall stress in the set of semiconductor layers at room temperature to be compressive and in a range between approximately 0.1 GPa and approximately 2.0 GPa.

2. The method of claim 1, wherein the growing the buffer structure includes adjusting the set of growth parameters to decrease local tensile stresses present during growth and to limit compressive stresses to approximately 1.0 GPa or less during growth.

3. The method of claim 1, wherein the growing the buffer structure includes growing the buffer layer directly on a substrate using a multi-stage process, wherein the multi-stage process includes:

growing a plurality of nucleation islands on the substrate; and

coalescing the plurality of nucleation islands into a single layer using a high growth temperature.

4. The method of claim 3, wherein the growing the plurality of nucleation islands uses a set of island growth conditions selected to grow nucleation islands having a target size and a target density, and wherein the set of island growth conditions includes:

a duration in a range of approximately one minute to approximately twenty minutes and a temperature in a range of approximately 600°

C. to approximately 1300°

C.

5. The method of claim 1, wherein the growing the buffer structure further includes:

selecting a target content for the intermediate layer based on at least one of;

stress or strain, of an existing heterostructure on which the intermediate layer is to be grown.

6. The method of claim 1, wherein the growing the buffer structure further includes:

measuring in-situ curvature of an existing heterostructure on which the intermediate layer is to be grown after the growing the buffer layer; and

determining at least one attribute of a material for the intermediate layer using the in-situ curvature, wherein the growing the intermediate layer uses a set of growth conditions selected based on the at least one attribute.

7. A method of fabricating a semiconductor device, the method including:

fabricating a semiconductor heterostructure for the semiconductor device, the fabricating including;

growing a buffer layer directly on a substrate using a multi-stage process, wherein the multi-stage process includes;

growing a plurality of nucleation islands formed of a group III nitride material on the substrate using a V/III ratio configured to form relatively small islands and a growth duration selected to increase a density of the plurality of nucleation islands, wherein the V/III ratio is in a range between approximately 100 to approximately 50000, and wherein the duration is in a range of approximately one minute to approximately twenty minutes;

inducing vertical growth of the plurality of nucleation islands using an increased growth temperature; and

coalescing the plurality of nucleation islands into a single layer using a high growth temperature, wherein the single layer is grown to a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

growing a set of group III nitride semiconductor layers on the buffer layer, wherein an overall stress in the set of group III nitride semiconductor layers at room temperature is compressive and in a range between approximately 0.1 GPa and approximately 2.0 GPa.

8. The method of claim 7, the fabricating the semiconductor heterostructure further including, prior to the growing the set of group III nitride layers, growing a group III nitride intermediate layer directly on the buffer layer, wherein the intermediate layer is configured to mitigate compression in the set of group III nitride layers.

9. The method of claim 8, wherein the intermediate layer includes a superlattice including a plurality of sub-layers having alternating tensile and compressive stresses.

10. The method of claim 8, the fabricating the semiconductor heterostructure further, prior to the growing the group III nitride intermediate layer:

measuring in-situ curvature of an existing heterostructure on which the intermediate layer is to be grown after the growing the buffer layer; and

determining at least one attribute of a material for the intermediate layer using the in-situ curvature, wherein the growing the intermediate layer uses a set of growth conditions selected based on the at least one attribute.

11. The method of claim 10, wherein the intermediate layer includes a plurality of sub-layers, and wherein the at least one attribute includes an aluminum molar fraction of a first sub-layer located directly on the buffer layer.

12. The method of claim 10, wherein the at least one attribute includes an average aluminum molar fraction for the intermediate layer.

13. The method of claim 7, wherein the device is an optoelectronic device.

14. A method of fabricating an optoelectronic device, the method including:

selecting a set of growth parameters for growing a buffer structure, wherein the set of growth parameters are configured to achieve a target effective lattice constant a for the buffer structure;

growing the buffer structure using the selected set of growth parameters directly on a substrate, wherein the growing the buffer structure includes;

growing a group III nitride buffer layer; and

growing a group III nitride intermediate layer directly on the buffer layer, wherein the intermediate layer includes a plurality of sub-layers having alternating tensile and compressive stresses, wherein the stresses are adjusted by varying a V/III ratio used during the growth of the plurality of sub-layers; and

growing a set of group III nitride semiconductor layers on the buffer structure, wherein the target effective lattice constant a causes an overall stress in the set of semiconductor layers at room temperature to be compressive and in a range between approximately 0.1 GPa and approximately 2.0 GPa.

15. The method of claim 14, wherein the growing the group III nitride buffer layer uses a multi-stage process, wherein the multi-stage process includes:

growing a plurality of nucleation islands formed of a group III nitride material on the substrate using a V/III ratio configured to form islands and a growth duration selected to increase a density of the plurality of nucleation islands, wherein the V/III ratio is in a range between approximately 100 to approximately 50000, and wherein the duration is in a range of approximately one minute to approximately twenty minutes;

inducing vertical growth of the plurality of nucleation islands using an increased growth temperature; and

coalescing the plurality of nucleation islands into a single layer, wherein the single layer is grown to a thickness in a range of approximately 100 Angstroms to approximately 100 microns.

16. The method of claim 14, wherein the growing the buffer structure further includes:

measuring in-situ curvature of an existing heterostructure on which the intermediate layer is to be grown after the growing the buffer layer; and

determining at least one attribute of a material for the intermediate layer using the in-situ curvature, wherein the growing the intermediate layer uses a set of growth conditions selected based on the at least one attribute.

17. The method of claim 16, wherein the at least one attribute includes an average aluminum molar fraction for the intermediate layer.

18. The method of claim 14, wherein the set of semiconductor layers includes:

an n-type layer located immediately adjacent to the intermediate layer;

an active region located on a side of the n-type layer opposite the intermediate layer; and

a p-type layer located on a side of the active region opposite the n-type layer.

19. The method of claim 18, wherein the active region is configured to emit ultraviolet radiation and has a threading dislocation density in a range of 1×

10³ to 5×

10⁹ threading dislocations per square centimeter.

20. The method of claim 14, wherein a dislocation density at a side of the buffer layer immediately adjacent to the intermediate layer is less than or equal to approximately 1×

10⁹ dislocation cores per square centimeter.