Chip or SoC including fusible logic array and functions to protect logic against reverse engineering

• US 9,413,356 B1
• Filed: 12/08/2014
• Issued: 08/09/2016
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: McKinley, Patrick A.
• Primary Examiner(s): Crawford, Jason M
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US14/563,071
• Time in Patent Office: 610 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G06K 15/4095 Secure printing computer driven secure printing G06F3/1238
• CPC Class Codes: H03K 19/17768 for security

Abstract

A security chip including a fusible logic array. An input is configured to receive, from a verification module external to the security chip, a seed value corresponding to one of a predetermined value and a generated value. The fusible logic array is configured to generate a logic result using the received seed value. The fusible logic array includes a logic gate configured to operate, based on a state of a fusible link within the logic gate, as both a first type of logic gate configured to perform a first logic operation and a second type of logic gate configured to perform a second logic operation different from the first logic operation. The fusible logic array is configured to generate the logic result based on the state of the fusible link. An output is configured to provide a key value, representative of the logic result, to the verification module.

Claims

1. A security chip, comprising:

an input configured to receive, from a verification module external to the security chip, a seed value, wherein the seed value corresponds to one of a predetermined value and a generated value;

a fusible logic array configured to generate a logic result using the received seed value, wherein

the fusible logic array includes a logic gate having structure corresponding to both i) a first type of logic gate configured to perform a first logic operation and ii) a second type of logic gate configured to perform a second logic operation different from the first logic operation,

the logic gate includes a fusible link located within the logic gate, wherein the logic gate is configured to operate, based on a state of the fusible link, as both the first type of logic gate and the second type of logic gate, and wherein the fusible link is arranged to conceal which of the first type of logic gate and the second type of logic gate the logic gate is configured as, and

the fusible logic array is configured to generate the logic result based on the state of the fusible link; and

an output configured to provide a key value, representative of the logic result, to the verification module external to the security chip.

2. The security chip of claim 1, wherein the security chip corresponds to a system-on-chip.

3. The security chip of claim 1, wherein fusible logic array includes a plurality of the logic gates, each of the logic gates including a respective fusible link of a plurality of the fusible links.

4. The security chip of claim 3, wherein i) a first logic gate of the plurality of logic gates is configured, using the respective fusible link of the first logic gate, to perform the first logic operation and ii) a second logic gate of the plurality of logic gates is configured, using the respective fusible link of the second logic gate, to perform the second logic operation.

5. The security chip of claim 3, wherein the plurality of logic gates includes i) a first plurality of logic gates each configured, using the respective fusible links of the first plurality of logic gates, to perform the first logic operation and ii) a second plurality of logic gates each configured, using the respective fusible links of the second plurality of logic gates, to perform the second logic operation.

6. The security chip of claim 1, wherein i) the first logic operation corresponds to a logical AND operation and ii) the second logic operation corresponds to a logical OR operation.

7. The security chip of claim 1, wherein the fusible link includes a one-time programmable fuse.

8. A printer cartridge including the security chip of claim 1.

9. A system including the security chip of claim 1, the system further comprising:

a printer cartridge, wherein the security chip is located on or within the printer cartridge; and

a printer, wherein the verification module is located within the printer.

10. A system including the security chip of claim 1 and further comprising:

the verification module; and

memory configured to store i) the seed value and ii) an expected key value corresponding to the seed value,

wherein the verification module is configured to i) receive the key value from the security chip, ii) compare the key value received from the security chip to the expected key value, and iii) selectively verify whether the security chip is authentic based on the comparison.

11. A method of operating security chip, the method comprising:

receiving, from a verification module external to the security chip, a seed value, wherein the seed value corresponds to one of a predetermined value and a generated value;

generating, using a fusible logic array, a logic result using the received seed value, wherein

the fusible logic array includes a logic gate having structure corresponding to both i) a first type of logic gate configured to perform a first logic operation and ii) a second type of logic gate configured to perform a second logic operation different from the first logic operation, and

the logic gate includes a fusible link located within the logic gate, wherein the logic gate is configured to operate, based on a state of the fusible link, as both the first type of logic gate and the second type of logic gate, and wherein the fusible link is arranged to conceal which of the first type of logic gate and the second type of logic gate the logic gate is configured as, and

generating the logic result includes generating the logic result based on the state of the fusible link; and

providing a key value, representative of the logic result, to the verification module external to the security chip.

12. The method of claim 11, wherein the security chip corresponds to a system-on-chip.

13. The method of claim 11, wherein fusible logic array includes a plurality of the logic gates, each of the logic gates including a respective fusible link of a plurality of the fusible links.

14. The method of claim 13, further comprising:

configuring a first logic gate of the plurality of logic gates, using the respective fusible link of the first logic gate, to perform the first logic operation; and

configuring a second logic gate of the plurality of logic gates, using the respective fusible link of the second logic gate, to perform the second logic operation.

15. The method of claim 13, further comprising:

configuring a first plurality of logic gates, using the respective fusible links of the first plurality of logic gates, to perform the first logic operation; and

configuring a second plurality of logic gates, using the respective fusible links of the second plurality of logic gates, to perform the second logic operation.

16. The method of claim 11, wherein i) the first logic operation corresponds to a logical AND operation and ii) the second logic operation corresponds to a logical OR operation.

17. The method of claim 11, wherein the fusible link includes a one-time programmable fuse.

18. The method of claim 11, wherein the security chip is located in a printer cartridge.

19. The method of claim 11, further comprising:

storing i) the seed value and ii) an expected key value corresponding to the seed value;

receiving the key value from the security chip;

comparing the key value received from the security chip to the expected key value; and

selectively verifying whether the security chip is authentic based on the comparison.