Efficient processing and detection of balanced codes

• US 9,413,384 B1
• Filed: 12/01/2015
• Issued: 08/09/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Cronie, Harm, Shokrollahi, Amin
• Primary Examiner(s): Lauture, Joseph
• Application Number:
  US14/956,021
• Time in Patent Office: 252 Days
• Field of Search: 341/58, 341/95, 375/295, 375/296, 375/259, 375/134, 714/776, 714/18, 714/787, 714/755
• US Class Current: 1/1
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 5/14 Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
• CPC Class Codes: H04B 1/7156 Arrangements for sequence synchronisation
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0048 in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder for spatial equalizer H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0059 Convolutional codes

Abstract

Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Claims

1. An apparatus comprising:

a tail current source connected to a common node, the tail current source configured to source a predetermined current;

a plurality of high-amplitude detection branches connected to the common node, each of the plurality of high-amplitude detection branches having an input node configured to receive via a multi-wire bus a respective element of a balanced-permutation modulation (PM) codeword having a predetermined number of high-amplitude values, and to divide the predetermined current among a number of conducting branches, the conducting branches being a subset of the plurality of high-amplitude detection branches, the conducting branches corresponding to high-amplitude detection branches receiving the predetermined number of high-amplitude values of the balanced-PM codeword.

2. The apparatus of claim 1, wherein the high-amplitude detection branches comprise NMOS transistors.

3. The apparatus of claim 2, wherein the high-amplitude values correspond to positive voltage signals.

4. The apparatus of claim 3, wherein the positive voltage signals correspond to ‘

+1’

elements of the balanced-PM codeword.

5. The apparatus of claim 1, wherein the high-amplitude detection branches comprise PMOS transistors.

6. The apparatus of claim 5, wherein the high-amplitude values correspond to negative voltage signals.

7. The apparatus of claim 6, wherein the negative voltage signals correspond to ‘

−

1’

elements of the balanced-PM codeword.

8. The apparatus of claim 1, wherein each high-amplitude detection branch further comprises an impedance element configured to provide a respective voltage output of a set of voltage outputs.

9. The apparatus of claim 8, further comprising a detector configured to receive the voltage outputs and to identify the elements of the balanced-PM codeword.

10. A method comprising:

receiving, via a multi-wire bus, elements of a balanced-permutation modulation (PM) codeword having a predetermined number of high-amplitude values; and

dividing a predetermined source current from a tail current source among a number of conducting branches, the conducting branches being a subset of a plurality of high-amplitude detection branches, the number of conducting branches determined by the predetermined number of high-amplitude values, the conducting branches corresponding to high-amplitude detection branches receiving the predetermined number of high-amplitude values of the balanced-PM codeword.

11. The method of claim 10, wherein the plurality of high-amplitude branches comprises transistors.

12. The method of claim 11, wherein the transistors are NMOS transistors.

13. The method of claim 12, wherein the high-amplitude values correspond to positive voltage signals.

14. The method of claim 13, wherein the positive voltage signals correspond to ‘

+1’

elements of the balanced-PM codeword.

15. The method of claim 11, wherein the transistors are PMOS transistors.

16. The method of claim 15, wherein the high-amplitude values correspond to negative voltage signals.

17. The method of claim 16, wherein the negative voltage signals correspond to ‘

−

1’

elements of the balanced-PM codeword.

18. The method of claim 10, further comprising generating voltage outputs using impedance elements in the plurality of high-amplitude branches.

19. The method of claim 18, further comprising identifying the elements of the balanced-PM codeword based on the voltage outputs.

20. A method comprising:

receiving elements of a first balanced-permutation modulation (PM) codeword via a multi-wire bus, the elements of the first balanced-PM codeword comprising a predetermined number of high-amplitude values;

dividing a predetermined source current from a tail current source among a first set of conducting branches, the first set of conducting branches being a subset of a plurality of high-amplitude detection branches, wherein a number of conducting branches in the first set is determined by the predetermined number of high-amplitude values, the first set of conducting branches corresponding to high-amplitude detection branches receiving the predetermined number of high-amplitude values of the first balanced-PM codeword;

receiving via the multi-wire bus, in a subsequent transmission interval, elements of a second balanced-PM codeword, the elements of the second balanced-PM codeword comprising the predetermined number of high-amplitude values; and

redirecting the predetermined source current from the tail current source from the first set of conducting branches to a second set of conducting branches, the second set of conducting branches being a subset of the plurality of high-amplitude detection branches, wherein a number of conducting branches in the second set is determined by the predetermined number of high-amplitude values, the second set of conducting branches corresponding to high-amplitude detection branches receiving the predetermined number of high-amplitude values of the second balanced-PM codeword.