Systems and methods for dimming control with capacitive loads

• US 9,414,455 B2
• Filed: 12/05/2014
• Issued: 08/09/2016
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: On-Bright Electronics (Shanghai) Co., Ltd. (Orthosie Investment Holdings Ltd.)
• Original Assignee: On-Bright Electronics (Shanghai) Co., Ltd. (Orthosie Investment Holdings Ltd.)
• Inventors: Zhou, Jun, Xiong, Zhongliang, Li, Miao, Cao, Yaming, Luo, Qiang, Fang, Lieyi
• Primary Examiner(s): Le, Tung X
• Application Number:
  US14/562,432
• Publication Number:
  US 20150091470A1
• Time in Patent Office: 613 Days
• Field of Search: 315/209.R, 315/219, 315224-226, 315/246, 315/247, 315/250, 315/291, 315/294, 315/297, 315/307
• US Class Current: 1/1
• CPC Class Codes: H05B 45/10 Controlling the intensity of the light
• CPC Class Codes: H05B 45/375 using buck topology

Abstract

System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal.

Claims

1. A system for dimming control, the system comprising:

a system controller including a first controller terminal and a second controller terminal;

a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal; and

a resistor including a first resistor terminal and a second resistor terminal;

wherein;

the system controller is configured to generate a first signal at the first controller terminal based at least in part on an input signal and to generate a second signal at the second controller terminal based at least in part on the first signal;

the first resistor terminal is coupled to the second transistor terminal;

the second resistor terminal is coupled to the third transistor terminal; and

the transistor is configured to receive the second signal at the first transistor terminal and to change between a first condition and a second condition in response to the second signal;

wherein;

the first signal is at a first logic level during a first period of time and changes between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time;

the second signal keeps at the second logic level during the first period of time and the third period of time; and

the second signal changes from the second logic level to the first logic level after the third period of time and remains at the first logic level during the fourth period of time.

2. The system of claim 1 wherein:

the second transistor terminal is biased at a first voltage; and

the first voltage changes with time.

3. The system of claim 1 wherein the transistor is configured to be turned on under the first condition and to be turned off under the second condition.

4. The system of claim 1 wherein the first logic level is a logic high level, and the second logic level is a logic low level.

5. The system of claim 1 wherein the first period of time is adjacent to the second period of time.

6. The system of claim 5 wherein:

the first period of time is adjacent to the third period of time; and

the third period of time is adjacent to the fourth period of time.

7. The system of claim 5 wherein:

the second period of time and the third period of time share a same starting time; and

the second period of time and the fourth period of time share a same ending time.

8. The system of claim 1 wherein:

at an ending time of the second period of time, the first signal becomes constant in magnitude at the first logic level; and

at a delayed time, the second signal becomes constant in magnitude at the second logic level, the delayed time being after the ending time.

9. The system of claim 1 wherein the first resistor terminal is coupled, directly, to the second transistor terminal.

10. The system of claim 1 wherein the second resistor terminal is coupled, directly, to the third transistor terminal.

11. A method for dimming control, the method comprising:

receiving an input signal;

generating a first signal based at least in part on the input signal;

generating a second signal based at least in part on the first signal;

receiving the second signal at a transistor; and

changing the transistor between a first condition and a second condition based at least in part on the second signal;

wherein;

the first signal is at a first logic level during a first period of time and changes between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time;

the second signal keeps at the second logic level during the first period of time and the third period of time; and

the second signal changes from the second logic level to the first logic level after the third period of time and remains at the first logic level during the fourth period of time.

12. The method of claim 11 wherein the changing the transistor between a first condition and a second condition includes:

turning on the transistor under the first condition; and

turning off the transistor under the second condition.

13. The method of claim 11 wherein the first logic level is a logic high level, and the second logic level is a logic low level.

14. The method of claim 11 wherein the first period of time is adjacent to the second period of time.

15. The method of claim 14 wherein:

the first period of time is adjacent to the third period of time; and

the third period of time is adjacent to the fourth period of time.

16. The method of claim 15 wherein:

the second period of time and the third period of time share a same starting time; and

the second period of time and the fourth period of time share a same ending time.

17. The method of claim 11 wherein:

at an ending time of the second period of time, the first signal becomes constant in magnitude at the first logic level; and

at a delayed time, the second signal becomes constant in magnitude at the second logic level, the delayed time being after the ending time.

18. A system controller for dimming control, the system controller comprising:

a first controller terminal; and

a second controller terminal;

wherein the system controller is configured to;

generate a first signal at the first controller terminal based at least in part on an input signal;

generate a second signal based at least in part on the first signal; and

output the second signal at the second controller terminal to change a transistor between a first condition and a second condition;

wherein;

the first signal is at a first logic level during a first period of time and changes between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time;

the second signal keeps at the second logic level during the first period of time and the third period of time; and

the second signal changes from the second logic level to the first logic level after the third period of time and remains at the first logic level during the fourth period of time.

19. The system controller of claim 18 wherein the first period of time is adjacent to the second period of time.

20. The system controller of claim 19 wherein:

the first period of time is adjacent to the third period of time; and

the third period of time is adjacent to the fourth period of time.

21. The system controller of claim 20 wherein:

the second period of time and the third period of time share a same starting time; and

the second period of time and the fourth period of time share a same ending time.

22. The system controller of claim 18 wherein:

at an ending time of the second period of time, the first signal becomes constant in magnitude at the first logic level; and

at a delayed time, the second signal becomes constant in magnitude at the second logic level, the delayed time being after the ending time.

23. A method for dimming control, the method comprising:

receiving an input signal;

generating a first signal based at least in part on the input signal, the first signal being at a first logic level during a first period of time and changing between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time;

generating a second signal based at least in part on the first signal; and

outputting the second signal, the second signal keeping at the second logic level during the first period of time and the third period of time, the second signal changing from the second logic level to the first logic level after the third period of time and remaining at the first logic level during the fourth period of time.

24. The method of claim 23 wherein the first period of time is adjacent to the second period of time.

25. The method of claim 24 wherein:

the first period of time is adjacent to the third period of time; and

the third period of time is adjacent to the fourth period of time.

26. The method of claim 25 wherein:

the second period of time and the third period of time share a same starting time; and

the second period of time and the fourth period of time share a same ending time.

27. The method of claim 23 wherein:

at an ending time of the second period of time, the first signal becomes constant in magnitude at the first logic level; and

at a delayed time, the second signal becomes constant in magnitude at the second logic level, the delayed time being after the ending time.

28. A system for dimming control, the system comprising:

a system controller including a first controller terminal, a second controller terminal, and a third controller terminal;

a first transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal; and

a first resistor including a first resistor terminal and a second resistor terminal;

wherein;

the system controller is configured to generate a first signal at the first controller terminal based at least in part on an input signal and to generate a second signal at the second controller terminal based at least in part on the first signal;

the second transistor terminal is coupled to the third controller terminal;

the first resistor terminal is coupled to the second transistor terminal;

the second resistor terminal is coupled to the third transistor terminal; and

the first transistor is configured to receive the second signal at the first transistor terminal and to change between a first condition and a second condition in response to the second signal.

29. The system of claim 28 wherein:

each period of the input signal includes a first part and a second part;

during the first part, the input signal changes with time in magnitude; and

during the second part, the input signal does not change with time in magnitude.

30. The system of claim 29 wherein the input signal is generated by a Triode for Alternating Current (TRIAC).

31. The system of claim 28 wherein the first transistor is an N-channel field effect transistor.

32. The system of claim 31 wherein the first transistor terminal is a gate terminal.

33. The system of claim 31 wherein the first transistor is configured to be turned on under the first condition and to be turned off under the second condition.

34. The system of claim 28 wherein the system controller is further configured to generate the first signal at a first logic level during a first period of time and to change the first signal between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time.

35. The system of claim 34 wherein the system controller is further configured to generate the second signal at the second logic level during the first period of time and the third period of time.

36. The system of claim 35 wherein the second signal changes from the second logic level to the first logic level after the third period of time.

37. The system of claim 36 wherein the second signal remains at the first logic level during the fourth period of time.

38. The system of claim 34 wherein the first logic level is a logic high level, and the second logic level is a logic low level.

39. The system of claim 28 wherein the first transistor terminal is coupled indirectly to the second controller terminal through a second resistor.

40. The system of claim 28, and further comprising:

a second transistor including a fourth transistor terminal, a fifth transistor terminal, and a sixth transistor terminal; and

a third transistor including a seventh transistor terminal, an eighth transistor terminal, and a ninth transistor terminal;

wherein;

the system controller further includes a fourth controller terminal biased at a first voltage;

the fourth transistor terminal is coupled to the second controller terminal;

the fifth transistor terminal is coupled to the seventh transistor terminal;

the sixth transistor terminal is coupled to the fourth controller terminal;

the eighth transistor terminal is coupled to the first transistor terminal; and

the ninth transistor terminal is biased at a second voltage.

41. The system of claim 40 wherein:

the sixth transistor terminal is coupled to the fourth controller terminal through a second resistor;

the seventh transistor terminal is coupled to the ninth transistor terminal through a third resistor; and

the fourth transistor terminal is coupled to the sixth transistor terminal through a fourth resistor, and coupled to the first transistor terminal through a fifth resistor.

42. The system of claim 41 wherein the first voltage changes with time.

43. The system of claim 28 wherein the system controller further comprises:

a sensing component configured to receive the first signal and to generate a logic signal based at least in part on the first signal; and

a control and driver component configured to detect the logic signal and to generate the second signal based at least in part on the logic signal.

44. The system of claim 28 wherein the second transistor terminal is coupled, directly, to the third controller terminal.

45. The system of claim 28 wherein the first resistor terminal is coupled, directly, to the second transistor terminal.

46. The system of claim 28 wherein the second resistor terminal is coupled, directly, to the third transistor terminal.

47. A system controller for dimming control, the system controller comprising:

a first controller terminal;

a second controller terminal; and

a third controller terminal;

wherein the system controller is configured to;

generate a first signal at the first controller terminal based at least in part on an input signal;

generate a second signal at the second controller terminal based at least in part on the first signal; and

output the second signal to a first transistor terminal of a transistor to change the transistor between a first condition and a second condition based at least in part on the second signal, a second transistor terminal of the transistor being coupled to the third controller terminal, a resistor being coupled between the second transistor terminal and a third transistor terminal of the transistor.