Slew rate and shunting control separation

• US 9,417,749 B2
• Filed: 10/30/2015
• Issued: 08/16/2016
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yu, Cheng-ho, Chang, Shih Chang, Bae, Hopil, Al-Dahle, Ahmad, Jamshidi-Roudbari, Abbas
• Primary Examiner(s): Edwards, Carolyn R
• Application Number:
  US14/929,120
• Publication Number:
  US 20160054834A1
• Time in Patent Office: 291 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact

Abstract

Setting a slew rate, e.g., a rising time or a falling time, of a scanning signal can be performed with a first operation, and a shunting resistance of the scanning line can be set with a second operation. A scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. A gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line.

Claims

1. A scanning system comprising:

a first gate line driver including;

a first scan line,

a first voltage line and a second voltage line,

a first p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the first scan line,

a first n-type transistor coupled to the second voltage line and the first scan line, the first n-type transistor configured to control a fall time of the first scan line by providing a first shunting resistance greater than a predetermined amount, and

a second n-type transistor coupled to the second voltage line and the first scan line, the second n-type transistor configured to provide a second shunting resistance less than the predetermined amount, wherein the first and second n-type transistors are both configured to be on when the second n-type transistor provides the second shunting resistance.

2. The scanning system of claim 1, wherein a gate of the p-type transistor is directly coupled to the gate of the first n-type transistor.

3. The scanning system of claim 1, wherein each scan line includes a first time period, a second time period, and a third time period,

the first time period configured for activating the p-type transistor,

the second time period configured for activating the first n-type transistor, and

the third time period configured for activating both the first n-type transistor and the second n-type transistor.

4. The scanning system of claim 3, wherein the third time period begins one clock period after the second time period begins.

5. The scanning system of claim 1, wherein the first n-type transistor is configured with a size of 10 um.

6. The scanning system of claim 1, wherein the second n-type transistor is configured with a size of 50 um.

7. The scanning system of claim 1, wherein the ratio of a size of the second n-type transistor to a size of the first n-type transistor is 5.

8. The scanning system of claim 1, wherein the scanning system is included in a touch screen, the touch screen comprising:

a plurality of sense regions including a plurality of first common electrodes;

a plurality of drive regions including a plurality of second common electrodes, wherein a parasitic capacitance between the plurality of second common electrodes and the scan line is different than a parasitic capacitance between the plurality of first common electrodes and the scan line.

9. The scanning system of claim 8, wherein an overlap between the plurality of first common electrodes and a plurality of scan lines is less than an overlap between the plurality of second common electrodes and the plurality of scan lines, and wherein the plurality of scan lines includes the scan line.

10. The scanning system of claim 1, further comprising:

a second gate line driver including;

a second scan line,

a second p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the second scan line,

a third n-type transistor coupled to the second voltage line and the second scan line, the third n-type transistor configured to control a fall time of the second scan line by providing the first shunting resistance, and

a fourth n-type transistor coupled to the second voltage line and the second scan line, the fourth n-type transistor configured to provide the second shunting resistance.

11. The scanning system of claim 10, wherein the first gate line driver further comprises a first latch configured to receive a third scan line and a first clock signal, one or more outputs of the first latch coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor.

12. The scanning system of claim 11, wherein the second gate line driver further comprises a second latch configured to receive the first scan line and a second clock signal, and wherein one or more outputs of the second latch are coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor.

13. A method of scanning a plurality of scan lines included a scanning system, the method comprising:

receiving a first voltage line;

connecting a scan line to a first voltage line through a first n-type transistor, in response to the first voltage line;

receiving a previous scan line and a first clock signal;

connecting the scan line to a second voltage line through a p-type transistor in response to the previous scan line and a rise of the first clock signal, the p-type transistor configured to control a rise time of the scan line;

connecting the scan line to the first voltage line through a first n-type transistor in response to the previous scan line and a fall of the first clock signal, the first n-type transistor configured to control a fall time of the scan line; and

connecting the scan line to the first voltage line through both the first n-type transistor and a second n-type transistor.

14. The method of claim 13, further comprising:

receiving a second clock signal;

connecting the scan line to the first voltage line through a second n-type transistor in response to a rise of the second clock signal, the second n-type transistor configured to provide a shunting resistance less than a predetermined amount.

15. The method of claim 14, wherein the scan line is coupled to the first voltage line through the first n-type transistor at a same time as the scan line is coupled to the first voltage line through the second n-type transistor.

16. The method of claim 13, further comprising disconnecting the scan line from the first voltage line when the scan line is connected to the second voltage line.

17. A system for driving one or more common electrode lines, the system comprising:

a first p-type transistor and a second p-type transistor, wherein a size of the second p-type transistor is larger than a size of the first p-type transistor; and

a first n-type transistor and a second n-type transistor, wherein a size of the second n-type transistor is larger than a size of the first n-type transistor.

18. The system of claim 17, wherein the first p-type transistor and second p-type transistor are configured for coupling a first common electrode line to a first voltage source.

19. The system of claim 18, wherein the first p-type transistor couples the first common electrode line to the first voltage source for a time period shorter than the second p-type transistor couples the first common electrode line to the first voltage source.

20. The system of claim 17, wherein the first n-type transistor and the second n-type transistor are configured for coupling a second common electrode line to a second voltage source.