Adaptive mapping of logical addresses to memory devices in solid state drives
First Claim
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1. A method for data storage, comprising:
- receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units;
obtaining respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in the memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit;
based on the estimates, adapting, by a processor, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and
storing the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units, and wherein adapting the mapping comprises modifying one or more of the weights, wherein modifying the weights comprises assigning, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands.
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Abstract
A method for data storage includes receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units. Respective estimates of a performance characteristic are obtained for the multiple memory units. A mapping, which maps the logical addresses to respective physical storage locations in the multiple memory units, is adapted based on the estimates so as to balance the performance characteristic across the memory units. The data items are stored in the physical storage locations in accordance with the adapted mapping.
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21 Claims
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1. A method for data storage, comprising:
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receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units; obtaining respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in the memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit; based on the estimates, adapting, by a processor, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and storing the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units, and wherein adapting the mapping comprises modifying one or more of the weights, wherein modifying the weights comprises assigning, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data storage apparatus, comprising:
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a memory interface configured to communicate with a memory that includes multiple memory units; and a processor coupled to the interface and configured to; receive data items associated with respective logical addresses for storage in the memory; obtain respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in the memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit; adapt, based on the estimates, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and store the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises the processor distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units and adapting the mapping by modifying one or more of the weights, wherein the processor is configured to assign, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A data storage apparatus, comprising:
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a memory comprising multiple memory units; and a processor coupled to the memory via a memory interface and configured to; receive data items associated with respective logical addresses for storage in the memory; obtain respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in that memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit; adapt, based on the estimates, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and store the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises the processor distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units and adapting the mapping by modifying one or more of the weights, wherein the processor is configured to assign, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands.
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Specification