System and method for memory block pool wear leveling
First Claim
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1. A method for memory block pool wear leveling in a nonvolatile memory system, the method comprising:
- identifying a plurality of memory block pools of the nonvolatile memory system, each of the memory block pools comprising a plurality of memory blocks and each of the plurality of memory blocks comprising a plurality of memory cells;
identifying a relaxation time delay for each of the plurality of memory block pools, wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum; and
executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools.
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Abstract
A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.
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Citations
21 Claims
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1. A method for memory block pool wear leveling in a nonvolatile memory system, the method comprising:
- identifying a plurality of memory block pools of the nonvolatile memory system, each of the memory block pools comprising a plurality of memory blocks and each of the plurality of memory blocks comprising a plurality of memory cells;
identifying a relaxation time delay for each of the plurality of memory block pools, wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum; and
executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- identifying a plurality of memory block pools of the nonvolatile memory system, each of the memory block pools comprising a plurality of memory blocks and each of the plurality of memory blocks comprising a plurality of memory cells;
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9. A nonvolatile memory controller for memory block pool wear leveling in a nonvolatile memory device, the nonvolatile memory controller comprising:
- a memory block pool wear leveling module configured for identifying a plurality of memory block pools of the nonvolatile memory device and for identifying a relaxation time delay for each of the plurality of memory block pools; and
a program/erase module coupled to the memory block pool wear leveling module, the program/erase module configured for executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools;
wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
- a memory block pool wear leveling module configured for identifying a plurality of memory block pools of the nonvolatile memory device and for identifying a relaxation time delay for each of the plurality of memory block pools; and
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17. A nonvolatile memory system for memory block pool wear leveling in a nonvolatile memory device, the nonvolatile memory system comprising:
- a nonvolatile memory storage module; and
a nonvolatile memory controller coupled to the nonvolatile memory storage module, the nonvolatile memory controller comprising;
a memory block pool wear leveling module configured for identifying a plurality of memory block pools of the nonvolatile memory system and for identifying a relaxation time delay for each of the plurality of memory block pools; and
a program/erase module coupled to the memory block pool wear leveling module, the program/erase module configured for executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools;
wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum. - View Dependent Claims (18, 19, 20, 21)
- a nonvolatile memory storage module; and
Specification