System and method for memory block pool wear leveling

• US 9,417,804 B2
• Filed: 07/07/2014
• Issued: 08/16/2016
• Est. Priority Date: 07/07/2014
• Status: Active Grant

• Current Assignee: Polaris PowerLED Technologies, LLC (Microchip Technology Incorporated)
• Original Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Inventors: Micheloni, Rino, Marelli, Alessia, Crippa, Luca
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US14/325,212
• Publication Number:
  US 20160004458A1
• Time in Patent Office: 771 Days
• Field of Search: 711/100, 711/103, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.

Claims

1. A method for memory block pool wear leveling in a nonvolatile memory system, the method comprising:

identifying a plurality of memory block pools of the nonvolatile memory system, each of the memory block pools comprising a plurality of memory blocks and each of the plurality of memory blocks comprising a plurality of memory cells;

identifying a relaxation time delay for each of the plurality of memory block pools, wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum; and

executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools.

2. The method of claim 1, wherein the relaxation time delay for each of the plurality of memory block pools of the nonvolatile memory device is equivalent.

3. The method of claim 1, wherein the identifying of the relaxation time delay for each of the plurality of memory block pools further comprises programming the plurality of memory blocks of each of the plurality of memory block pools in a first pattern, reading the programmed memory blocks to identify errors, and identifying the relaxation time delay for each of the memory block pools as the end of a relaxation phase for the memory blocks in the respective memory block pool.

4. The method of claim 1, wherein executing the predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools further comprises, evenly distributing the execution of the predetermined number of program/erase cycles among the plurality of blocks of the memory block pool.

5. The method of claim 1, wherein identifying the plurality of memory block pools of the nonvolatile memory system further comprises randomly identifying the plurality of memory blocks for each of the plurality of memory blocks pools.

6. The method of claim 1, wherein identifying the plurality of memory block pools of the nonvolatile memory system further comprises:

identifying the BER (bit error rate) for each of the plurality of memory blocks; and

identifying each of the plurality of memory blocks as belonging to one of the plurality of memory block pools based upon the BER of the memory block.

7. The method of claim 1, wherein the identifying the relaxation time delay for each of the plurality of memory block pools further comprises:

programming the plurality of memory blocks of one or more of the plurality of memory block pools in a one or more patterns, reading the programmed memory blocks to identify errors, and identifying the relaxation time delay for each of the memory block pools using a retention time corresponding to the end of the relaxation phase of each of the one or more patterns.

8. The method of claim 7, wherein the identifying the relaxation time delay for each of the plurality of memory block pools further comprises identifying the relaxation time delay that is greater than or equal to the lowest retention time of the retention time corresponding to the end of the relaxation phase of each of the one or more patterns and less than or equal to the highest retention time of the retention time corresponding to the end of the relaxation phase of each of the one or more patterns.

9. A nonvolatile memory controller for memory block pool wear leveling in a nonvolatile memory device, the nonvolatile memory controller comprising:

a memory block pool wear leveling module configured for identifying a plurality of memory block pools of the nonvolatile memory device and for identifying a relaxation time delay for each of the plurality of memory block pools; and

a program/erase module coupled to the memory block pool wear leveling module, the program/erase module configured for executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools;

wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum.

10. The controller of claim 9, wherein the relaxation time delay for each of the plurality of memory block pools of the nonvolatile memory device is equivalent.

11. The controller of claim 9, wherein the relaxation time delay is a time that is within a relaxation phase for a nonvolatile memory device.

12. The controller of claim 9, wherein the predetermined number of program/erase cycles for each of the plurality of memory block pools is equivalent.

13. The controller of claim 9, wherein executing the predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools further comprises, evenly distributing the execution of the predetermined number of program/erase cycles among a plurality of blocks for each of the plurality of memory block pools.

14. The controller of claim 9, wherein the memory block pool wear leveling module is further configured for randomly identifying a plurality of memory blocks for each of the plurality of memory blocks pools.

15. The controller of claim 9, wherein the memory block pool wear leveling module is further configured for identifying the bit error rate (BER) for each of a plurality of memory blocks and for identifying each of the plurality of memory blocks as belonging to one of the plurality of memory block pools based upon the bit error rate of the memory block.

16. The controller of claim 9, wherein the memory block pool wear leveling module is configured for programming a plurality of memory blocks of each of the plurality of memory block pools in one or more patterns, reading the programmed memory blocks to identify errors, and identifying the relaxation time delay for each of the memory block pools using a retention time corresponding to the end of a relaxation phase of each of the one or more patterns.

17. A nonvolatile memory system for memory block pool wear leveling in a nonvolatile memory device, the nonvolatile memory system comprising:

a nonvolatile memory storage module; and

a nonvolatile memory controller coupled to the nonvolatile memory storage module, the nonvolatile memory controller comprising;

a memory block pool wear leveling module configured for identifying a plurality of memory block pools of the nonvolatile memory system and for identifying a relaxation time delay for each of the plurality of memory block pools; and

a program/erase module coupled to the memory block pool wear leveling module, the program/erase module configured for executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of each of the plurality of memory block pools;

wherein the relaxation time delay for each of the plurality of memory block pools is identified as a duration of time between a completion of a programming cycle of the memory block pool and a point in time when BER (bit error rate) of the memory block pool is at a minimum.

18. The nonvolatile memory system of claim 17 wherein the identified relaxation time delay for each pool is less than or equal to a retention time at which data retention has resulted in a transition of the same number of cells from an erased state to a programmed state as have transitioned from a programmed state to an erased state for one or more test pattern.

19. The nonvolatile memory system of claim 17, wherein the relaxation time delay is a time that is within a relaxation phase for one or more nonvolatile memory device in the nonvolatile memory storage module.

20. The nonvolatile memory system of claim 17, wherein the relaxation time delay is a time that is within the last forty percent of a relaxation phase for one or more nonvolatile memory device in the nonvolatile memory storage module.

21. The nonvolatile memory system of claim 17, wherein the memory block pool wear leveling module is configured for programming a plurality of memory blocks of each of the plurality of memory block pools in one or more patterns, reading the programmed memory blocks to identify errors, and identifying the relaxation time delay for each of the memory block pools using a retention time corresponding to the end of a relaxation phase of each of the one or more patterns.