Serial multiply accumulator for galois field

• US 9,417,848 B2
• Filed: 03/28/2014
• Issued: 08/16/2016
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: StorArt Technology (Shenzhen) Co., Ltd.
• Original Assignee: StorArt Technology (Shenzhen) Co., Ltd.
• Inventors: Hung, Jui Hui, Yen, Chih Nan
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US14/228,763
• Publication Number:
  US 20150277857A1
• Time in Patent Office: 872 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10

Abstract

A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Claims

1. A serial multiply accumulator for operation of two multiplications and one addition over Galois field, comprising:

a first element feeding circuit for sequentially outputting first elements in the Galois field per clock cycle;

a second element feeding circuit for sequentially outputting second elements in the Galois field per clock cycle;

a plurality of first calculating circuits, linked successively from upstream to downstream, each receiving the first element, the second element, one third element, and one fourth element per clock cycle, receiving an operating data from an upstream-linked first calculating circuit, optionally receiving a feedback data, producing two products by multiplying the first element by the third element and multiplying the second element by the fourth element, and outputting another operating data downstream, the outputted operating data being available from adding one product to the other, adding the products to the received operating data, adding the products to the feedback data, or adding the products and the received operating data to the feedback data, wherein the first calculating circuit arranged most upstream doesn'"'"'t receive the operating data from other first calculating circuit; and

a second calculating circuit, linked to the first calculating circuit arranged the most downstream, for receiving the first element, the second element, one third element, and one fourth element per clock cycle, receiving the outputted operating data from the linked first calculating circuit, producing two products by multiplying the first element by the third element and multiplying the second element by the fourth element, and outputting the feedback data, the outputted operating data being available from adding one product to the other or adding the products to the received operating data;

wherein the first elements, the second elements, the third elements and the fourth elements have the same amount, the third element provided to one of the first calculating circuit or the second calculating circuit is different from that provided to other first calculating circuits, and the fourth element provided to one of the first calculating circuit or the second calculating circuit is different from that provided to other first calculating circuits.

2. The serial multiply accumulator according to claim 1, further comprising:

a third element feeding circuit, linked to each of the first calculating circuit and the second calculating circuit, for providing a specified third element thereto; and

a fourth element feeding circuit, linked to each of the first calculating circuit and the second calculating circuit, for providing a specified fourth element thereto.

3. The serial multiply accumulator according to claim 1, wherein coefficients of a polynomial correspond to the first calculating circuits sequentially with a constant coefficient corresponding to the most upstream first calculating circuit.

4. The serial multiply accumulator according to claim 3, wherein the feedback data is provided to one first calculating circuit if a corresponding coefficient of that first calculating circuit is not zero.

5. The serial multiply accumulator according to claim 3, wherein if the amount of the first calculating circuits and the second calculating circuit is equal to or less than the number of the greatest power of the polynomial, at least one coefficient of higher power of the polynomial doesn'"'"'t correspond to one first calculating circuit.

6. The serial multiply accumulator according to claim 1, wherein the first calculating circuit further comprises:

a first AND gate for multiplying the first element by the third element;

a second AND gate for multiplying the second element by the fourth element;

a first XOR gate for adding one product to the other, adding the products to the received operating data, adding the products to the feedback data, or adding the products and the received operating data to the feedback data; and

a first register for temporarily storing the operating data from the first XOR gate for one clock cycle.

7. The serial multiply accumulator according to claim 1, wherein the second calculating circuit further comprises:

a third AND gate for multiplying the first element by the third element;

a fourth AND gate for multiplying the second element by the fourth element;

a second XOR gate for adding one product to the other or adding the products to the received operating data; and

a second register for temporarily storing the operating data from the third XOR gate for one clock cycle.