Data-detector circuit for RFID tags

• US 9,418,258 B2
• Filed: 12/20/2012
• Issued: 08/16/2016
• Est. Priority Date: 02/27/2012
• Status: Active Grant

• Current Assignee: Centro Nacional de Tecnologia Eletronica Avancada-Ceitec SA
• Original Assignee: Ceitec SA
• Inventors: Henes Neto, Egas, Courcelle, Laurent
• Primary Examiner(s): Frech, Karl D
• Application Number:
  US14/381,254
• Publication Number:
  US 20150154425A1
• Time in Patent Office: 1,335 Days
• Field of Search: 235/435, 235/439, 235/451
• US Class Current: 1/1
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 7/10009 sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Data-detector circuit for RFID labels, wherein the package is detected using two circuits, a polarizing circuit and a polarized circuit. The polarization signal can be sent from the polarizing circuit to the polarized circuit via a low-pass filter. The reference signal for comparison with the package detected is generated on the basis of the package attenuated by means of a voltage splitter. The reference signal is filtered via a low-pass filter. The resulting circuit has the characteristics of low consumption and high sensitivity.

Claims

1. A data detector circuit comprising:

a polarizing detector circuit (15) that receives an input data signal to be detected (27) producing a polarization voltage signal (29);

a polarized detector circuit (14) that receives said input data signal to be detected (21) and that receives said polarization voltage signal (22), producing a voltage signal reflecting an envelope (23) of said input signal to be detected (21).

2. The data detector circuit of claim 1 wherein said polarizing detector circuit (15) receives as input at least one signal that depends on the signal received by an antenna (13).

3. The data detector circuit of claim 2 wherein the output of said polarizing detector circuit (15) is connected to a polarization input of said polarized detector circuit (14).

4. The data detector circuit of claim 2 wherein said polarizing detector circuit output (15) is connected to a polarization input of said polarized detector circuit (14) via a low-pass filter (16).

5. The data detector circuit of claim 4 wherein a polarized detector output signal (14) is used to generate an average signal (11) after being attenuated by a voltage divider (17) and filtered by a low-pass filter (18).

6. The data detector circuit of claim 5 wherein the data being detected by a comparator circuit which compares a detected envelope signal (7) at said polarized detector output (14) with said average signal (11) to generate detected data (12) at a data detector circuit output (20).

7. The data detector circuit of claim 6 wherein said detected data (12) at said data detector circuit output (20) is fed back (44) to a pair of low-pass filters (16, 18), with a detected data (12) controlling an external signal (37) in said low-pass filters to turn off an on/off switch (38) of a current source i2 (39).

8. The data detector circuit of claim 1 wherein said polarizing detector circuit (15) is comprised of a PMOS transistor (31) with the source terminal of the transistor connected to an input (27) of said polarizing detector (15) and with the drain terminals and transistor gate connected to an output (29) of said polarizing detector (15).

9. The data detector circuit of claim 1 wherein said polarized detector circuit (14) is comprised of a PMOS transistor (25) with the source terminal of the transistor connected to the signal input (21) of said polarized detector (14), with the transistor gate terminal connected to the polarization input (22) of said polarized detector (14) and with the drain terminal of the transistor connected to the output of said polarized detector (23).

10. A data detector circuit comprising:

a polarizing detector circuit (15) that receives an input data signal to be detected (27) producing a polarization voltage signal (29);

a polarized detector circuit (14) that receives said input data signal to be detected (21) and that receives said polarization voltage signal (22), producing a voltage signal reflecting an envelope (23) of said input signal to be detected (21);

wherein said polarizing detector circuit (15) is comprised of a PMOS transistor (31) with the source terminal of the transistor connected to an input (27) of said polarizing detector (15) and with the drain terminals and transistor gate connected to an output (29) of said polarizing detector (15); and

wherein said polarized detector circuit (14) is comprised of a PMOS transistor (25) with the source terminal of the transistor connected to the signal input (21) of said polarized detector (14), with the transistor gate terminal connected to the polarization input (22) of said polarized detector (14) and with the drain terminal of the transistor connected to the output of said polarized detector (23).

11. The data detector circuit of claim 10 wherein said polarizing detector circuit output (15) is connected to the polarization input (22) of the polarized detector circuit (14).

12. The data detector circuit of claim 10 wherein the polarizing detector circuit output (15) is connected to the polarization input (22) of the polarized detector circuit (14) via a low-pass filter (16).

13. The data detector circuit of claim 10 wherein the polarized detector output signal (14) is used to generate an average signal (11) after being attenuated by a voltage divider (17) and filtered by a low-pass filter (18).

14. The data detector circuit of claim 13 wherein the data being detected by a comparator circuit that compares a detected envelope signal (7) at the polarized detector output (14) with the average signal (11) obtained to generate the detected data (12) at a circuit output (20).

15. The data detector circuit of claim 14 characterized by using the detected data (12) at the circuit output (20) is fed back to the low-pass filters (16, 18), with the detected data (12) controlling an external signal (37) in the low-pass filters to turn off an on/off switch (38) of the i2 current source (39).