IC layout pattern matching and classification system and method

• US 9,418,289 B2
• Filed: 09/11/2013
• Issued: 08/16/2016
• Est. Priority Date: 02/12/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gabrani, Maria, Hurley, Paul T.
• Primary Examiner(s): Newman, Michael A
• Application Number:
  US14/023,790
• Publication Number:
  US 20140010436A1
• Time in Patent Office: 1,070 Days
• Field of Search: 382/145, 382/144, 382/147, 382/149, 382/191, 382/224, 382/260, 382/276
• US Class Current: 1/1
• CPC Class Codes: G03F 7/70616 Monitoring the printed patterns
• CPC Class Codes: G06F 18/22 Matching criteria, e.g. proximity measures
• CPC Class Codes: G06F 2218/06 by applying a scale-space analysis, e.g. using wavelet analysis
• CPC Class Codes: G06F 2218/16 by matching signal segments
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G06T 7/66 of image moments or centre of gravity
• CPC Class Codes: G06V 30/422 Technical drawings; Geographical maps

Abstract

A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.

Claims

1. A method for classifying patterns in a set of layout patterns, comprising:

computing a plurality of moments for each of a plurality of pattern windows of an integrated circuit layout, wherein the set of layout patterns is provided using a hardware scanner; and

classifying the pattern windows into pattern classes using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows, wherein the patterns include one or more components of a layout, wherein classifying reveals a set of patterns for inclusion in a permissible set of patterns for a given technology node.

2. The method as recited in claim 1, further comprising decomposing the pattern windows using a wavelet analysis, wherein the wavelet analysis includes decomposing the pattern windows using Haar wavelets.

3. The method as recited in claim 1, wherein computing a plurality of moments for each pattern window includes computing one or more of a mean, a variance, a skewness and a kurtosis.

4. The method as recited in claim 1, wherein classifying the pattern windows using a distance computation includes classifying the pattern windows using a Canberra metric.

5. The method as recited in claim 1, further comprising computing the moments for a plurality of levels, and the step of classifying the pattern windows using a distance computation for respective moments of the pattern windows includes classifying the pattern windows using a distance computation for respective moments of the pattern windows in the plurality of levels.

6. The method as recited in claim 5, wherein the levels include frequency components in one or more orientations.

7. The method as recited in claim 6, wherein the orientations include one or more of horizontal, vertical and diagonal.

8. The method as recited in claim 1, further comprising reducing the set of layout patterns by identifying, matching and classifying the patterns into functional equivalence classes.

9. A non-transitory computer readable storage medium comprising a computer readable program for classifying patterns in a set of layout patterns, wherein the computer readable program when executed on a computer causes the computer to perform steps of as recited in claim 1.

10. An integrated circuit chip configured to perform a method for classifying patterns in a set of layout patterns, the method as recited in claim 1.

11. The method as recited in claim 1, wherein the plurality of moments are computed using a low frequency component of a wavelet analysis as an approximation.

12. A method for classifying patterns in a set of layout patterns, comprising:

computing a plurality of moments for each of a plurality of pattern windows of an integrated circuit layout using a low frequency component of a wavelet analysis as an approximation, wherein the set of layout patterns is provided using a hardware scanner; and

classifying the pattern windows into pattern classes using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows, wherein classifying reveals a set of patterns for inclusion in a permissible set of patterns for a given technology node.

13. The method as recited in claim 12, wherein the wavelet analysis includes decomposing the pattern windows using Haar wavelets.

14. The method as recited in claim 12, wherein computing a plurality of moments for each pattern window includes computing one or more of a mean, a variance, a skewness and a kurtosis.

15. The method as recited in claim 12, wherein classifying the pattern windows using a distance computation includes classifying the pattern windows using a Canberra metric.

16. The method as recited in claim 12, further comprising computing the moments for a plurality of levels, and the step of classifying the pattern windows using a distance computation for respective moments of the pattern windows includes classifying the pattern windows using a distance computation for respective moments of the pattern windows in the plurality of levels.

17. The method as recited in claim 16, wherein the levels include frequency components in one or more orientations.

18. The method as recited in claim 17, wherein the orientations include one or more of horizontal, vertical and diagonal.

19. The method as recited in claim 12, further comprising reducing the set of layout patterns by identifying, matching and classifying the patterns into functional equivalence classes.

20. A non-transitory computer readable storage medium comprising a computer readable program for classifying patterns in a set of layout patterns, wherein the computer readable program when executed on a computer causes the computer to perform steps of as recited in claim 12.