Integrated circuit with on-die decoupling capacitors

• US 9,418,873 B2
• Filed: 08/24/2014
• Issued: 08/16/2016
• Est. Priority Date: 08/24/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kumar, Shailesh, Garg, Vikas, Varshney, Sumit, Verma, Chetan
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/467,039
• Publication Number:
  US 20160056099A1
• Time in Patent Office: 723 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

Claims

1. A semiconductor device, comprising:

an integrated circuit (IC) die including a processor having first and second interfaces, at least one decoupling capacitor, at least one capacitor pad connected to the decoupling capacitor, first and second internal connection pads connected respectively to the first and second interfaces, at least one intermediate connection pad, and a plurality of die bonding pads;

a package for the semiconductor die having electrical contacts for connection to external electrical circuitry;

a plurality of external connection members comprising first bond wires that connect respective die bonding pads with the package electrical contacts;

at least one internal connection member selectively connecting the decoupling capacitor by way of the first or the second internal connection pad and the capacitor pad for decoupling the first or the second interface respectively, and

wherein the internal connection member comprises second bond wires that respectively connect the intermediate connection pad to the capacitor pad, and the selected internal connection pad to the intermediate connection pad.

2. The semiconductor device of claim 1, wherein the first and second interfaces have first and second power distribution lines respectively, and the first and second internal connection pads are connected to the first and second power distribution lines respectively.

3. The semiconductor device of claim 1, wherein the second bond wires for the selected one of the first and the second interfaces operationally connect the die bonding pads with the package electrical contacts and the internal connection pads with the capacitor pad of the die, and leave floating die bonding pads and the internal connection pads of the other one of the first and the second interfaces.

4. A semiconductor integrated circuit (IC) die, comprising:

a processor including first and second interfaces;

die bonding pads for connection to external electrical contacts of a package for the die;

at least one decoupling capacitor;

at least one capacitor pad connected to the decoupling capacitor; and

first and second internal connection pads respectively connected to the first and second interfaces for connection by at least one internal connection member alternatively to the capacitor pad for decoupling the first or the second interface,

wherein;

the die bonding pads are connectable by first bond wires to the external contacts,

the internal connection pads are connectable by at least one second bond wire alternatively to the capacitor pad,

the IC die also includes at least one intermediate connection pad that is connectable by a third bond wire to the capacitor pad, and

the internal connection pads are connectable alternatively by the at least one second bond wire to the intermediate connection pad.

5. The semiconductor die of claim 4, wherein the first and second interfaces have first and second power distribution lines respectively, and the first and second internal connection pads are connected to the first and second power distribution lines respectively.