Silicon germanium and silicon fins on oxide from bulk wafer

• US 9,418,900 B1
• Filed: 07/15/2015
• Issued: 08/16/2016
• Est. Priority Date: 07/15/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: He, Hong, Loubet, Nicolas, Kuss, James, Wang, Junli
• Primary Examiner(s): Dulka, John P
• Application Number:
  US14/800,290
• Time in Patent Office: 398 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence

Abstract

A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Claims

1. A method for forming fins for complementary metal oxide semiconductor (CMOS) devices, comprising:

growing a SiGe layer followed by a silicon layer over a surface of a bulk Si substrate;

patterning fin structures from the silicon layer and the SiGe layer;

filling between the fin structures with a dielectric fill;

forming trenches through the dielectric fill, the fin structures and into the substrate, the trenches including a cut perpendicular to the fin structures to expose end portions of the fin structures;

blocking off a first region of the fin structures with a dielectric layer;

removing the SiGe layer of the fin structures of a second region by selectively etching the fin structures from the end portions of the fin structures to form voids;

filling the voids with dielectric material;

exposing the silicon layer of the fin structures in the first and second regions; and

thermally oxidizing the SiGe layer in the first region to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

2. The method as recited in claim 1, wherein the first region is configured for P-type field effect transistors (PFETs) and the second region is configured for N-type field effect transistors (NFETs).

3. The method as recited in claim 1, wherein growing the SiGe layer followed by the silicon layer over a surface of a bulk Si substrate includes epitaxially growing the SiGe layer over the entire bulk substrate to provide increased quality of the SiGe layer.

4. The method as recited in claim 1, wherein forming trenches through the dielectric fill includes forming trenches in a direction parallel to the fin structures.

5. The method as recited in claim 1, wherein blocking off the first region of the fin structures with the dielectric layer includes blocking off the first region of the fin structures with a bilayer dielectric layer including an oxide layer and a nitride layer.

6. The method as recited in claim 1, wherein removing the SiGe layer of the fin structures of the second region by selectively etching the fin structures from the end portions includes performing a wet etch with HCl.

7. The method as recited in claim 1, wherein thermally oxidizing the SiGe layer in the first region includes converting the SiGe layer to an oxide material to form the oxide layer in the first region.

8. The method as recited in claim 1, wherein removing the SiGe layer of the fin structures of the second region includes removing the SiGe layer from below the silicon layer to expose a lower surface of the silicon layer in the voids.

9. A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices, comprising:

growing a SiGe layer over a surface of a bulk Si substrate;

growing a silicon layer on the SiGe layer;

forming a first dielectric layer on the silicon layer;

patterning fin structures from the silicon layer and the SiGe layer;

filling between the fin structures with a dielectric fill;

forming trenches through the dielectric fill, the fin structures and into the substrate, the trenches including a cut perpendicular to the fin structures to expose end portions of the fin structures;

blocking off a first region of the fin structures with a second dielectric layer;

removing the SiGe layer of the fin structures of a second region by selectively etching the fin structures from the end portions of the fin structures to form voids;

filling the voids with dielectric material;

exposing the fin structures in the first and second regions;

forming spacers on the fin structures;

thermally oxidizing the SiGe layer in the first region to drive Ge into the silicon layer in the first region to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region; and

removing the spacers.

10. The method as recited in claim 9, wherein the first region is configured for P-type field effect transistors (PFETs) and the second region is configured for N-type field effect transistors (NFETs).

11. The method as recited in claim 9, wherein growing the SiGe layer includes epitaxially growing the SiGe layer over the entire bulk substrate to provide increased quality of the SiGe layer.

12. The method as recited in claim 9, wherein forming trenches through the dielectric fill includes forming trenches in a direction parallel to the fin structures.

13. The method as recited in claim 9, wherein blocking off the first region of the fin structures with the dielectric layer includes blocking off the first region of the fin structures with a bilayer dielectric layer including an oxide layer and a nitride layer.

14. The method as recited in claim 9, wherein removing the SiGe layer of the fin structures of the second region by selectively etching the fin structures from the end portions includes performing a wet etch with HCl.

15. The method as recited in claim 9, wherein thermally oxidizing the SiGe layer in the first region includes converting the SiGe layer to an oxide material to form the oxide layer in the first region.

16. The method as recited in claim 9, wherein removing the SiGe layer of the fin structures of the second region includes removing the SiGe layer from below the silicon layer to expose a lower surface of the silicon layer in the voids.

17. The method as recited in claim 9, further comprising forming source and drain regions.

18. The method as recited in claim 17, wherein the first dielectric layer remains on the silicon layer to protect against fin erosion up the step of forming source and drain regions.

19. The method as recited in claim 9, wherein the first dielectric layer includes silicon nitride.

20. The method as recited in claim 9, wherein filling the voids with dielectric material includes densifying the dielectric material.