Protrusion bump pads for bond-on-trace processing

• US 9,418,928 B2
• Filed: 08/07/2014
• Issued: 08/16/2016
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Yu-Min, Wu, Jiun Yi
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US14/453,858
• Publication Number:
  US 20150194405A1
• Time in Patent Office: 740 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16157 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Claims

1. A method comprising:

providing a carrier substrate comprising;

a core; and

a first conductive layer on the core;

forming a first bump pad on the first conductive layer, wherein the first bump pad and the first conductive layer comprise different conductive materials;

forming a first conductive trace, wherein the first conductive trace comprises;

a first portion on the first conductive layer; and

a second portion on the first bump pad;

forming a first dielectric layer on the first conductive layer, the first bump pad, and the first conductive trace;

removing the core; and

removing the first conductive layer using an etching process, wherein the etching process further recesses the first portion of the first conductive trace from a top surface of the first dielectric layer.

2. The method of claim 1, wherein the first conductive trace and the first conductive layer comprise a same conductive material, and wherein the first bump pad is an etch stop layer during etching process.

3. The method of claim 2, wherein the first conductive trace and the first conductive layer comprise copper, wherein the first bump pad comprises nickel or tin, and wherein the etching process comprises using a hydrogen peroxide or sulfuric acid based chemical etchant.

4. The method of claim 1 further comprising, after removing the first conductive layer:

providing an integrated circuit chip comprising a conductive bump; and

physically coupling the conductive bump to the first bump pad.

5. The method of claim 1, wherein after removing the first conductive layer, a top surface of the first bump pad is substantially level with the top surface of the first dielectric layer.

6. The method of claim 1, wherein forming the first bump pad comprises:

forming a first patterned mask layer on the first conductive layer, wherein the first patterned mask layer comprises a first opening exposing the first conductive layer;

filling the first opening with a different conductive material than the first conductive layer; and

removing the first patterned mask layer.

7. The method of claim 1, wherein forming the first bump pad comprises:

forming a second patterned mask layer on the first conductive layer and the first bump pad, wherein the second patterned mask layer comprises a second opening exposing the first conductive layer and the first bump pad;

filling the second opening with a same conductive material as the first conductive layer; and

removing the second patterned mask layer.

8. The method of claim 1, wherein the carrier substrate further comprises a second conductive layer on an opposing side the core as the first conductive layer, and wherein the method further comprises:

forming a second bump pad on the second conductive layer, wherein the second bump pad and the second conductive layer comprise different conductive materials;

forming a second conductive trace, wherein the second conductive trace comprises;

a third portion on the second conductive layer; and

a fourth portion on the second bump pad;

forming a second dielectric layer on the second conductive layer, the second bump pad, and the second conductive trace;

removing the core; and

removing the second conductive layer using an etching process, wherein the etching process further recesses the third portion of the second conductive trace from a surface of the second dielectric layer.

9. A method comprising:

providing integrated circuit chip comprising a plurality of conductive bumps;

providing an apparatus comprising;

a dielectric layer;

a plurality of bump pads in the dielectric layer; and

a plurality of conductive traces in the dielectric layer, wherein the plurality of conductive traces each comprise;

a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer; and

a second portion, wherein at least one of the plurality of bump pads covers the second portion; and

bonding the integrated circuit chip to the apparatus by physically coupling the plurality of conductive bumps to the plurality of bump pads.

10. The method of claim 9, wherein providing apparatus comprises:

forming the plurality of bump pads on a conductive layer, wherein the plurality of bump pads and the conductive layer comprise different conductive materials;

forming the plurality of conductive traces on the plurality of bump pads and the conductive layer, wherein the plurality of conductive traces and the conductive layer comprise a same conductive material; and

removing the conductive layer using an etching process, wherein the etching process further recesses each of the first portions of the plurality of conductive traces from the top surface of the dielectric layer, and wherein the plurality of bump pads are etch stop layers during the etching process.

11. The method of claim 10, wherein the plurality of bump pads comprise nickel or tin, wherein the conductive layer and the plurality of conductive traces comprise copper, and wherein the etching process comprises using a hydrogen peroxide or sulfuric acid based chemical etchant.

12. The method of claim 9, wherein top surfaces of the plurality of bump pads are at least as high as a top surface of the dielectric layer.

13. The method of claim 9, wherein bonding the integrated circuit chip to the apparatus comprises not physically coupling any of the plurality of conductive bumps to the first portions of the plurality of conductive traces.

14. A method comprising:

providing a carrier substrate comprising a core;

forming a dielectric layer comprising a first conductive trace and a second conductive trace over the carrier substrate;

removing the core;

forming a bump pad on the first conductive trace; and

recessing a top surface of the second conductive trace below a top surface of the dielectric layer.

15. The method of claim 14, wherein the bump pad comprises a different material than the first conductive trace.

16. The method of claim 15, wherein forming the dielectric layer comprising the first conductive trace and the second conductive trace comprises:

after forming the bump pad, patterning a first mask to define a first opening and a second opening over the carrier substrate, wherein the first opening exposes the bump pad, and wherein the second opening exposes the carrier substrate;

forming the first conductive trace in the first opening;

forming the second conductive trace in the second opening;

removing the first mask; and

depositing a dielectric layer over and extending along sidewalls of the first conductive trace, the second conductive trace, and the bump pad.

17. The method of claim 15, wherein recessing the top surface of the second conductive trace comprises using an etching chemical that selectively etches the second conductive trace at a faster rate than the bump pad.

18. The method of claim 14, wherein the carrier substrate further comprises a conductive layer over the core, wherein forming the bump pad comprises:

removing first portions of the conductive layer; and

using a second mask to cover a second portion of the conductive layer on the first conductive trace while removing the first portions of the conductive layer.

19. The method of claim 18, wherein recessing the top surface of the second conductive trace comprises using the second mask to cover the bump pad during recessing the top surface of the second conductive trace.

20. The method of claim 18, wherein forming the bump pad further comprising:

removing the second mask;

patterning a third mask over the dielectric layer, wherein the third mask comprises an opening exposing the second portion of the conductive layer; and

forming a conductive material in the opening on the second portion of the conductive layer.