Chip stack with electrically insulating walls

• US 9,418,976 B2
• Filed: 03/17/2015
• Issued: 08/16/2016
• Est. Priority Date: 01/21/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Colgan, Evan G., Nah, Jae-Woong
• Primary Examiner(s): SMITH, ZANDRA V
• Assistant Examiner(s): Parker, John M
• Application Number:
  US14/660,035
• Publication Number:
  US 20150187739A1
• Time in Patent Office: 518 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/0348 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/03914 the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/08112 the bonding area being at least partially embedded in the surface of the body
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/10165 : Alignment aids
• CPC Class Codes: H01L 2224/10175 : Flow barriers
• CPC Class Codes: H01L 2224/11312 : Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13013 : being rectangular or square
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13084 : Four-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1601 : Structure
• CPC Class Codes: H01L 2224/16113 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16503 : comprising an intermetallic compound
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
• CPC Class Codes: H01L 2224/81139 : Guiding structures on the body
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8181 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers polymers per se C08; polymer adhesives C09J
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/20641 : larger or equal to 100 microns less than 200 microns
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging

Abstract

A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Claims

1. A chip stack, comprising:

two or more chips; and

a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and comprising a pad, the pad comprising;

an outer surface portion disposed at a single plane outwardly from a conductor and on upper-most surfaces of insulators such that the outer surface portion is insulated from the conductor, and

an inner surface portion recessed from the single plane of the outer surface and disposed in contact with the conductor,

the chip stack further comprising insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint, the insulating walls extending from the entirely uppermost surfaces of the corresponding insulators, abutting outer edges of the outer surface portion of the pad and being displaced from each of the corresponding adjacent ones of the solder pads.

2. The chip stack according to claim 1, wherein the solder joint occupies about 50% or more of the area of the chip stack.

3. The chip stack according to claim 1, wherein the solder joint and the adjacent solder joint have a pitch of about 100 microns or less.

4. The chip stack according to claim 1, wherein the insulating walls are disposed on each of the two or more chips.

5. A chip stack element, comprising:

a substrate having two major surfaces;

solder pads arrayed along a plane of one of the major surfaces with outer surface portions thereof disposed outwardly from a conductor and above insulators such that the outer surface portions are insulated from the conductor, the solder pads comprising a seed layer, a post disposed on the seed layer, solder joint material and underbump metallurgy interposed between the solder joint material and the post; and

walls formed of electrically insulating material disposed between adjacent ones of the solder pads,

wherein for each solder pad, the walls extend from entirely uppermost surfaces of the insulators, abut outer edges of the outer surface portions, are displaced from each of the adjacent ones of the solder pads, surround the seed layer, the post and the underbump metallurgy and form with the underbump metallurgy a solder joint material containing recess.

6. The chip stack element according to claim 5, wherein the solder pads occupy more than about 25-30% of an area of the one major surface.

7. The chip stack element according to claim 5, wherein the solder pads occupy more than about 50% of an area of the one major surface.

8. The chip stack element according to claim 5, wherein the solder pads have a pitch of about 100 microns or less.

9. The chip stack element according to claim 5, wherein the walls form a hexagonal array.

10. The chip stack element according to claim 5, wherein the walls are continuous and comprise polymer.

11. The chip stack element according to claim 5, wherein the walls are displaced outwardly from and above the solder pads and, for each solder pad, the seed layer, the post and the underbump metallurgy are wider than the solder joint material.